Investigation of asynchronous pipeline circuits based on bundled-data encoding: Implementation styles, behavioral modeling, and timing analysis

Abstract

As VLSI technology enters the post-Moore era, there has been an increasing interest in asynchronous design because of its potential advantages in power consumption, electromagnetic emission, and automatic speed scaling capacity under supply voltage variations. In most practical asynchronous circuits, a pipeline forms the micro-architecture backbone, and its characteristics play a vital role in determining the overall circuit performance.In this paper, we investigate a series of typical asynchronous pipeline circuits based on bundled-data encoding, spanning different handshake signaling protocols such as 2-phase (micropipeline, Mousetrap, and Click), 4-phase (simple, semi-decoupled, and fully-decoupled), and single-track (GasP). An in-depth review of each selected circuit is conducted regarding the handshaking and data latching mechanisms behind the circuit implementations, as well as the analysis of its performance and timing constraints based on formal behavior models. Overall, this paper aims at providing a survey of asynchronous bundled-data pipeline circuits, and it will be a reference for designers interested in experimenting with asynchronous circuits.

Discrete Dynamic Modeling Analysis of Data Mining Algorithm under the Background of Big Data in the Strategic Goal of Sustainable Development of College Physical Training

“…Secondly, the principle of Apriori algorithm is simple and easy to realize the research requirements. Finally, the college students' physical fitness data, training intensity data, test score data, and after-school exercise data collected in college physical training have strong correlation and complex internal relationship, so it is suitable to use Apriori algorithm to establish discrete dynamic modeling [16].…”