Investigation of Buried-Well Potential Perturbation Effects on SEU in SOI DICE-Based Flip-Flop Under Proton Irradiation

Sakamoto, Kazumitsu; Baba, Shigeo; Kobayashi, Daisuke; Okamoto, Shogo; Shindou, H.; Kawasaki, Osamu; Makino, Takahiro; Mori, Y.; Matuura, Daisuke; Kusano, Masaki; Narita, Takanori; Ishii, Shigeru; Hirose, Kazuyuki

doi:10.1109/tns.2020.2969651

Cited by 3 publications

(1 citation statement)

References 24 publications

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“…The conventional D flip-flop is susceptible to SEU [22,23]. A common hardening technique involves replacing the dualinverter latch in the flip-flop with a robust storage cell, such as the popular Dual Interlocked Storage Cell (DICE) [24] or Quatro [25].…”

Section: Introductionmentioning

confidence: 99%

A low power consumption and cost-efficient SEU-tolerant pulse-triggered flip-flop design

Jin

Zhang

et al. 2021

IEICE Electron. Express

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A power-efficient Single Event Upset (SEU) -tolerant pulsetriggered flip-flop design is presented. The dual-modular redundant design takes advantage of concise formation of pulse-triggered designs, and avoids the disadvantages of it, such as high power consumption. Clock-gating scheme is applied to reduce power consumption. The static configuration and the avoidance of contention mechanism led to the balance of power consumption, speed and SEU tolerance. The SEU tolerance is evaluated by means of SEU cross section, which is significantly lower than conventional D flip-flop. The proposed flip-flop is designed in 55nm CMOS technology to evaluate performances. The proposed design achieves the lowest power consumption, which is even lower than conventional D flip-flop. Although the speed is sacrificed, the lowest power-delay product is achieved among hardened designs. The proposed design provides solution to speedinsensitive and power-constrained applications.

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Section: Introductionmentioning

confidence: 99%

A low power consumption and cost-efficient SEU-tolerant pulse-triggered flip-flop design

Jin

Zhang

et al. 2021

IEICE Electron. Express

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Single event upset reinforcement technology of DICE flip-flop based on layout design

Lai

Jian

et al. 2022

西北工业大学学报

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D flip-flop is the basis of timing logic circuit, and SEMU phenomenon tends to be serious with the integrated circuit process size shrinking to nanometer scale. The anti-SEU ability based on DICE structure for D flip-flop cannot meet the requirements of aerospace engineering. Based on the SEU reinforcement technology of D flip-flop under nano-technology and the SEU mechanism of DICE structure, a layout-level anti-SEU flip-flop design method based on DICE circuit structure is proposed considering the circuit performance, area, power consumption and other resource costs. And then a D flip-flop with SEU resistance is designed by commercial 65 nm process, and the designed flip-flop area is 1.8 times that of commercial structure flip-flop. The function and and radiation simulation results indicate that the establishment time and transmission delay of the flip-flop are equivalent to those of the commercial one, and no SEU occurs under the Ge ion bombardment with the LET threshold of approximately 37 MeV·cm2/mg. The performance of the flip-flop circuit and the ability to resist single particle soft error are excellent. In the anti-radiation ASIC design, the area, wiring resources and timing overhead caused by the reinforcement of the D flip-flop circuit are greatly saved.

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Mitigation of Single-Event Upset Sensitivity for 6T SRAM in a 0.18 μm DSOI Technology Considering High LET Heavy Ions Irradiation

Wang,

Chen,

Liu

et al. 2024

IEEE Trans. Nucl. Sci.

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Investigation of Buried-Well Potential Perturbation Effects on SEU in SOI DICE-Based Flip-Flop Under Proton Irradiation

Cited by 3 publications

References 24 publications

A low power consumption and cost-efficient SEU-tolerant pulse-triggered flip-flop design

A low power consumption and cost-efficient SEU-tolerant pulse-triggered flip-flop design

Single event upset reinforcement technology of DICE flip-flop based on layout design

Mitigation of Single-Event Upset Sensitivity for 6T SRAM in a 0.18 μm DSOI Technology Considering High LET Heavy Ions Irradiation

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