Investigation of Charge-plasma Based Dopingless Tunnel FET for Analog/RF and Linear Applications

Sharma, Suruchi; Basu, Rikmantra; Kaur, Baljit

doi:10.1007/s12633-021-01514-5

Cited by 3 publications

(3 citation statements)

References 48 publications

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“…Figure 7(B) shows that AG HJ DLTFET provides insignificantly more

{normalC}_{gd}

than SG HJ DL TFET. The increased density of conduction states causes the enhanced capacitive coupling in AG HJ DL TFET and as a result, it provides larger

{normalC}_{gd}

for higher gate voltage 32 …”

Section: Simulation Results and Discussionmentioning

confidence: 99%

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Device and circuit level performance assessments of gate engineered Ge/GaAs heterojunction doping less TFET

Som,

Jana

2023

Int J Numerical Modelling

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Recently, the doping‐less tunnel FET has gained popularity due to its lower process complexity than conventional TFETs with heavily doped source and drain regions. In this literature, we have introduced a symmetric gate Ge/GaAs heterojunction doping‐less TFET(SG HJ DL TFET) using 4.6 eV work function for both the top gate and bottom gate and an asymmetric gate Ge/GaAs heterojunction doping‐less TFET (AG HJ DL TFET) using 3.9 eV work function as top gate and 4.6 eV work function as a bottom gate. A comparative study has been performed between these two devices. The back gate misalignment engineering in the AG HJ DL TFET induces higher charge plasma near the source‐channel junction which will enhance the drain current. Due to a larger drain current, an improved ratio (11.8 times), and steeper SS (37%) are achieved in optimized AG HJ DL TFET than SG HJ DL TFET. Furthermore, the Analog/Radio Frequency and linearity performance parameters have been examined, and a significant improvement is noticed in the optimized AG HJ DL TFET. The impact of different interface trap charges (ITCs) on device performances is also investigated and it is found that AG HJ DL TFET shows more immunity to ITCs than SG HJ DL TFET. Finally, the Verilog‐A‐based model has been developed for the AG HJ DL TFET to utilize its circuit‐level behavior. The optimized device‐based Common Source amplifier (CS amplifier) has been simulated in the Cadence Virtuoso tool. The AG HJ DL TFET‐based CS amplifier offers a 6.83% improvement in voltage gain over the other reported work.

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“…Figure 7(B) shows that AG HJ DLTFET provides insignificantly more

{normalC}_{gd}

than SG HJ DL TFET. The increased density of conduction states causes the enhanced capacitive coupling in AG HJ DL TFET and as a result, it provides larger

{normalC}_{gd}

for higher gate voltage 32 …”

Section: Simulation Results and Discussionmentioning

confidence: 99%

“…The increased density of conduction states causes the enhanced capacitive coupling in AG HJ DL TFET and as a result, it provides larger C gd for higher gate voltage. 32 (A) (B)…”

Section: Analysis Of Analog/rf Parametersmentioning

confidence: 99%

Device and circuit level performance assessments of gate engineered Ge/GaAs heterojunction doping less TFET

Som,

Jana

2023

Int J Numerical Modelling

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“…Table 4 presents the comparison of present DMG-HJLTFET device with the recently designed TFET devices, 15,36 showing the superior RF performance of DMG-HJLTFET.…”

Section: Comparative Analog/rf Performance Analysismentioning

confidence: 99%

Impact of tunnel gate process variations on analog/radio frequency (microwave) and small signal parameters of hetero‐material tunneling interfaced charge plasma junctionless tunnel field effect transistor

Sharma

Chaujar

2022

Circuit Theory & Apps

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This paper proposes a dual metal gate, hetero-material tunneling interfaced junctionless tunnel field effect transistor (TFET), (DMG-HJLTFET), utilizing III-V compound semiconducting materials, InAs (low band-gap source material)/GaAs (higher band-gap channel and drain material) by applying the band-gap and dual material gate engineering. The 2-D TCAD simulations have been executed to explore the impact of tunnel gate process variations-work function and length on DC and analog figure of merits (FOMs) of DMG-HJLTFET. The extracted result parameters have also been compared to SMG (single metal gate)-HJLTFET and conventional Si-JLTFET. The DMG-HJLTFET attains improved ON current in the range of 88.5 Â 10 À6 A/μm and OFF current remains as low as 2.89 Â 10 À16 A/μm. It exhibits a high current switching ratio of 3.1 Â 10 11 as compared to SMG-HJLTFET (I ON = 24 Â 10 À6 A/μm and I ON /I OFF = 1.4 Â 10 11 ) and Si-JLTFET (I ON = 7 Â 10 À6 A/μm and I ON /I OFF = 1.8 Â 10 6 ). Further, the radio frequency/microwave (RF) parameters such as power gains (h 12 , UPG, and Gma), f max , and GBP have been compared for all three aforementioned devices. Moreover, the small signal admittance (Y) parameters have been examined to explore the possible scope of DMG-HJLTFET for future internet of everything communications and fast switching applications.

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Partially Extended Germanium Source DG-TFET: Design, Analysis, and Optimization for Enhanced Digital and Analog/RF Parameters

Singh

Vaithiyanathan

Kaur

2022

Silicon

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Investigation of Charge-plasma Based Dopingless Tunnel FET for Analog/RF and Linear Applications

Cited by 3 publications

References 48 publications

Device and circuit level performance assessments of gate engineered Ge/GaAs heterojunction doping less TFET

Device and circuit level performance assessments of gate engineered Ge/GaAs heterojunction doping less TFET

Impact of tunnel gate process variations on analog/radio frequency (microwave) and small signal parameters of hetero‐material tunneling interfaced charge plasma junctionless tunnel field effect transistor

Partially Extended Germanium Source DG-TFET: Design, Analysis, and Optimization for Enhanced Digital and Analog/RF Parameters

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