Investigation of Cl₂etch in view of extremely low temperature selective epitaxial processes

Abstract

A Cl 2 etch of different group IV materials in a low temperature range (260-600 °C) is presented. It is shown that in general the Cl 2 etching behavior is very similar to that of HCl: Si is etched slowest, Ge fastest with SiGe being between these two cases. Activation energies for Cl 2 etching of Si, SiGe and Ge are very low and show that neither Cl nor H surface passivation are limiting factors for the etch. The etching rate is strongly affected by the choice of the carrier gas (He, H 2 and N 2 ) and by the process pressure which gives high flexibility for its application. As compared to HCl, Cl 2 allows decreasing of the etching process temperatures down to ∼400 °C for Si and ∼250 °C for Ge. Although it is not clear if co-flow selective processes are visible due to possible exothermic chain reaction of radicals in the presence of group IV hydrides, cyclic approaches can be relatively easily achieved at temperatures below 500 °C.

Low‐Temperature Selective Growth of Heavily Boron‐Doped Germanium Source/Drain Layers for Advanced pMOS Devices

“…For this reason, one needs to combine the low‐temperature nonselective epitaxy with an etching process which will selectively suppress the parasitic polycrystalline materials. Since HCl, the typical etchant used in epi processes to realize selective epitaxial growth, is totally inefficient for Ge etching below 400 °C, we have considered Cl 2 , which has revealed to be much more aggressive. Thanks to the low process temperature and reduced pressure, we nevertheless mitigate the “aggressiveness” of Cl 2 etching toward Ge and identify a process window allowing to setup a controllable and reproducible CDE routine.…”

Source/Drain Materials for Ge nMOS Devices

“…This behavior is due to the aggressive etch rates of Ge in comparison to Si when using Cl 2 as etchant gas. 9 None of the studied materials alone could fulfill all Ge nMOS S/D requirements. The newly evaluated n-Ge 1−x Sn x and the n-Si y Ge 1−x−y Sn x layers (despite relatively low resistivities values as compared to Si:P layers) could not provide r c values below 1 × 10 −7 Ω.cm 2 .…”

“…It must be noted that although, the in − situ P-doped Si grown with Si 3 H 8 at low temperature and directly on Ge, provides the highest active carrier concentration (3.5 × 10 20 cm −3 ) and the lowest ρ c values (7.5 × 10 −9 Ω.cm 2 ), the Si:P layers still cannot be implemented at S/D level in n-Ge FinFET devices due to the non-selective nature of the growth process. The implementation of a cyclic deposition and etch (CDE) approach using Cl 2 gas as an etchant, which is specially required for low thermal budget processes since the conventional HCl etching does not work 9 , results in a low etching selectivity. The etching process fails to remove the amorphous Si:P from oxide or nitride surfaces with high etch rates and simultaneously preserve the crystalline material (i.e.…”

“…This result is attributed to the aggressive etching of Ge as compared to Si while using Cl 2 as an etchant gas. 9 Meanwhile, other S/D materials such as n-Ge, n-Ge 1−x Sn x , n-Si y Ge 1−x−y Sn x can be grown selectively without the need for CDE approach, but the amount of active dopants in the as-grown layers are limited to the mid 10 19 cm −3 range. 10 Consequently, the lowest contact resistivity values achievable with these materials are limited to ∼10 −5 -10 −6 Ω.cm 2 .…”

Very Low Temperature Epitaxy of Group-IV Semiconductors for Use in FinFET, Stacked Nanowires and Monolithic 3D Integration

“…down to ∼ 350°C for Si 0.5 Ge 0.5 . 11 We considered different combinations of precursors and etchants as described in the following paragraphs. p-type SiGe.-Highly B-doped Si 1-x Ge x (with 40% ≤ x ≤ 70%) materials are often regarded as the best option for the epitaxy of S/D for pMOS Si devices.…”