Investigation of error types associated with failures in multicore processors

Abstract

RésuméCet article est la continuation d'un portefeuille de recherche sur la sécurité des composants sur étagère, dont l'utilisation se répand dans les systèmes avioniques complexes (Condra, 2014). Parmi les composants complexes sur étagère, les processeurs multicoeurs sont l'un des plus étudiés pour leur impact potentiel sur la sécurité associée à l'indéterminisme (Bieth, 2013). Un article précédent (Jean, 2015) discuta des aspects temporels ainsi que des méthodes pour déterminer le Worst-case Execution Time (WCET). Cet article se concentre sur la détermination des types d'erreurs spécifiques des processeurs multicoeurs, la détermination de leurs effets, les moyens de détection et de mitigation de ces erreurs, ainsi que l'existence de critères pour contenir la panne résultante ou pour récupérer de cette erreur. SummaryThis paper is a continuation of a research thrust on safety assurance for Commercial Off-the-Shelf (COTS) which use is becoming widely spread in complex avionics (Condra, 2014). Among complex COTS, multicore processors are one of the components being investigated in terms of their potential safety impacts relative to non-determinism (Bieth, 2013). A previous paper (Jean, 2015) addressed timing issues and the methods to determine Worst-case Execution Time (WCET). The present paper focuses on the determination of error types specific to multicore processors, the determination of the effects of these failure modes, the means of detection and mitigation of these errors, and the existence of criteria for containment of the resulting failure or recovery from the error.

Identification of Multi-Core Interference

“…To the best of our knowledge, few works have proposed solutions for resource usage 3. Researchers from Thales have proposed the Initiator-Target Model [6,14,17,18] to help identify the interference channels on multi-core chips. Their model is very simple, but suffers from a combinatorial explosion.…”

“…The initiator-target model has been introduced in [6] and reused in [14,17], and [18]. The goal was to provide a theoretical view for the identification of the interference channels (called performance contentions in [6]) that can occur in a multi-core processor.…”