Investigation of inherent wafer defects using reflection grating technique

Abstract

The ecomony scale of return for semiconductor wafers can be attributed to 2 factors i.e.1) number of systems that is crammed onto a wafer and 2) substitution of precious metal (Au) to other material for the wafer backmetal. Any of these 2 changes will be a major challenge to semiconductor wafer dicing yield. Crack die with a random order is a great myth to be dicovered. In this study, Moire Techniques is being adopted to perform the upfront analysis on the crack die to minimize the yield loss during dicing process. In this study we focus and to corellate 3 different wafers with different size (5", 6" and 8") and backmetal (bare silicon, Au and AuX). The effect of the backside metallization to the die strength has been numerically and experimentally investigated. These results obtained is being made to optimise the dicing method to obtain a homogenous stresses across the wafer.