Investigation of parasitic bipolar transistor in rail-based electrostatic discharge (ESD) protection circuits

Abstract

In this paper, ESD triggering mechanism of the parasitic PNP bipolar transistor in rail-based ESD protection circuits was investigated. The device simulation results show that the triggering voltage of the parasitic PNP varies with the geometry of the base region (e.g., the spacing between P+ and N-well). Furthermore, the test structures of parasitic PNP devices with different width of collector and base region were fabricated using the 65 nm low-k logic/Mixed-Mode CMOS process and characterized with the transmission line pulse (TLP) system. Both simulation and experimental results demonstrated that the triggering voltage of parasitic PNP structures has strong dependence on the base region and the simulation results also show that the triggering voltage is significantly affected by the spacing between P-well and N-well.

Investigation of soft ESD failure on capacitive transimpedance amplifier for hybrid integrated infrared sensor

“…For its catastrophic consequence, electrostatic discharge (ESD) induced hard failures such as thermal breakdowns of microelectronic device and metal interconnect, have been well understood and drawn much attention of the researchers in the world [1,2,3,4,5,6,7,8]. Nevertheless, the problems of ESD induced soft failure such as performance degradation and increased leakage current, are still not fully comprehended and investigated [9,10,11,12].…”