2007 International Symposium on Semiconductor Manufacturing 2007
DOI: 10.1109/issm.2007.4446875
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Investigation of PDA process to improve electrical characteristics of HfO<inf>x</inf>N<inf>y</inf> High-k dielectric formed by ECR plasma oxidation of HfN

Abstract: In this paper, post deposition annealing (PDA) processes such as Si wafer covering rapid thermal annealing (SWC-RTA) and rapid cooling process were investigated to improve electrical characteristics of HfO x N y films formed by ECR Ar/O 2 plasma oxidation of ultra-thin HfN films. An EOT of 0.96 nm with leakage current density of 0.26 A/cm 2 was obtained by utilizing SWC-RTA and rapid cooling. The obtained result shows the smallest equivalent oxide thickness (EOT) for the HfO x N y film formed by ECR plasma pro… Show more

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Cited by 5 publications
(3 citation statements)
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“…Then, 10 nm-thick metallic-phase HfN 0.5 gate electrode ( HfN : 4.8 eV) was in-situ deposited on HfN 1.3 (I) using Ar/N 2 gas flow ratio of 10/0.2 sccm (N 2 : 2%, 0.09 Pa). The µ-wave/RF power was 500/400 W. The PMA was carried out at 500°C/10 min in N 2 /4.9%H 2 FG ambient (1 SLM) by silicon-wafer-covering (SWC) process utilizing rapid thermal annealing (RTA) system [14].…”
Section: Methodsmentioning
confidence: 99%
“…Then, 10 nm-thick metallic-phase HfN 0.5 gate electrode ( HfN : 4.8 eV) was in-situ deposited on HfN 1.3 (I) using Ar/N 2 gas flow ratio of 10/0.2 sccm (N 2 : 2%, 0.09 Pa). The µ-wave/RF power was 500/400 W. The PMA was carried out at 500°C/10 min in N 2 /4.9%H 2 FG ambient (1 SLM) by silicon-wafer-covering (SWC) process utilizing rapid thermal annealing (RTA) system [14].…”
Section: Methodsmentioning
confidence: 99%
“…In contrast, for HfN oxidation, HfN (5 nm) was deposited at 0.15, 0.17, and 0.19 Pa by adjusting Ar/N 2 flow rate (20/0.8, 22.5/0.9, and 25/1 sccm, respectively) and oxidized at 0.18 Pa (Ar/O 2 flow rate of 20/8 sccm, m-wave power of 500 W) for 15 -60 s. Postdeposition annealing (PDA) was performed by silicon-wafer-covering rapid thermal annealing (SWC-RTA) at 800 C for 1 min in N 2 ambient. 14) The Al electrodes were evaporated onto the samples through a shadow mask (: 100 mm). The fabricated MOS diodes were characterized by capacitance-voltage (C-V) and current-voltage (J-V) methods.…”
Section: Methodsmentioning
confidence: 99%
“…Next, post deposition annealing (PDA) was carried out at 600°C/1 min in N 2 ambient by Si wafer covering (SWC) process utilizing rapid thermal annealing system (RTA) [15]. Finally, Al contact layer was ex-situ deposited by evaporation, and gate electrode patterning was carried out for Al/HfN 0.5 to fabricate MONOS diode structures as shown in Fig.…”
Section: Introductionmentioning
confidence: 99%