Investigation of Spacer Engineering on n-Type Field Effect Transistor Performance during Laser Spike Annealing

Abstract

A new liner oxide spacer structure of n-type field effect transistors (n-FETs) with a favorable stress optimum has been investigated to improve the crystallization in the amorphous area of the source–drain extension (SDE) implantation during laser spike annealing. The dopant activation performance of n+ polycrystalline silicon is identical to the sheet resistance judgement for two spacer schemes of n-FETs devices, but the junction leakage of the oxide liner spacer is lower than that of the conventional composite spacer. The stress within SDE depth induced by the spacer is changed from compressive to tensile stress when the conventional composite spacer was replaced by the oxide liner spacer.