Investigation of Step Fin (SF), Step Drain (SD) and Step Source (SS) FinFETs with Trap Effect

Das, Rinku Rani; Maity, Santanu; Chowdhury, Arijit; Chakraborty, Apurba

doi:10.1080/03772063.2022.2071770

Cited by 1 publication

(1 citation statement)

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“…This random variation is due to the dependence of the metal-work function (WF) on the crystal orientation of the metal grain, which is very difficult to control during fabrication [6,7]. The presence of ITCs increased the thermal density, which affects the Self-heating and deteriorates the device performance and device's reliability at stake [8][9][10]. Channel engineering is one of the ways to mitigate SCEs, and dual material gate (DMG) technology further suppresses SCEs without affecting the device behavior [11,12].…”

Section: Introductionmentioning

confidence: 99%

Physical insights of interface traps and self-heating effect on electrical response of DMG FinFETs in overlap and underlap configurations: analog/RF perspective

Chaudhary,

Saha

2023

Phys. Scr.

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This paper presents a thorough analysis on analog/RF parameters including interface trap charges (ITCs) of two different densities of states (DOS) along with self-heating on the performance of DMG FinFETs in Overlap and Underlap configurations. Initially, the independent simulations for acceptor ITCs and Self-heating in conventional device reveals that performance degradation caused by Self-heating is more prominent (25.03%) than uniform acceptor ITCs (9.46%). In consecutive step, the cumulative impact of both acceptor ITCs and Self-heating on DC and RF/analog parameters are carried out. Investigation reveals that as the impact of self-heating is larger in overlap configuration, the degradation in drain current is higher in overlap configuration (45.2%, 54.5%) as compared to conventional (30.4%, 40.96%) and underlap (37.2%, 52.8%) configurations for both Uniform and Gaussian trap distributions, respectively.

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