Investigation of the Factors Affecting the Warpage Prediction of Multi-Chip Package

Rajmane, Pavan; Karthikeyan, D.; Schwarz, M. Philip; Syed, Ahmer

doi:10.1109/ectc32696.2021.00240

Cited by 1 publication

(1 citation statement)

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“…Temperature causes thermal stress, and temperature mismatch is the main cause of the warping of microsystem structures [24]. Warpage and stress are the main causes of microsystem failure which affects reliability and yield, so it has become a research hotspot and attracted countless scholars [25][26][27][28][29][30]. However, most of the above studies discuss only the single-physics problem, and fail to obtain the results of multi-physics coupling, which are obviously deviated from the actual situation.…”

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confidence: 99%

Design and Simulation of a System-in-Package Chip for Combined Navigation

Yang,

Shi,

Jin

2024

Micromachines

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This paper proposes a system-in-package combination navigation chip. We used wire bonding, chip stacking, surface mount, and other processes to integrate satellite navigation chips, inertial navigation chips, microprocessor chips, and separation devices. Finally, we realized the hardware requirements for combined navigation in a 20 mm × 20 mm chip. Further, we performed a multi-physics simulation analysis of the package design. For antenna signals, the insertion loss was greater than −1 dB@1 GHz and the return loss was less than −10 dB@1 GHz. The amplitude of these noises of the signal between the MCU and the IMU was approximately 20%, and the maximum value of the coupling coefficient between signal lines on the top surface was 13.4174%. The ninth mode of the power plane yielded a maximum voltage of 55 mV, and all power delivery networks had a DC voltage drop of less than 2%. The highest temperature in the microsystem was approximately 42 °C. These results show that our design performed well in terms of signal, power, and thermal performance.

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