Investigation of the internal noises in the chip with orthogonal topology of power supply feeding

In this paper the problem of increasing the reliability of the designed devices, implemented on the matrix VLSI has been considered. The proposed approach consists in the choosing of the special area in the chip during mapping procedure at the packaging level. Using of such approach allows for designer to obtain more optimal topology solution, and thus will increase the reliability of designed devices.

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“…The basic results are cited in [3] and [4]. It allows to make the computational investigation of the MM.…”

Section: Internal Noises In the Matrix Vlsi Chipmentioning

confidence: 99%

Approach to solve the reliability problem at packaging level in the matrix VLSI

Vasiltsov¹,

Mandziy²,

Bench³

2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)

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Frequency domain simulation of the EM internal noises in the matrix VLSI with orthogonal topology of power supply feeding

Vasiltsov

Mandziy

2002 3rd International Symposium on Electromagnetic Compatibility

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Software simulation of the noise distribution in the chip

Vasiltsov¹,

Mandzij²,

Bench³

et al.

IEEE International Symposium on Electromagnetic Compatibility

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In this paper the problem of sofmare simulation of the noise distribution in the chip has been considered. On the basis of earlier developed analytical equations the internal electromagnetic noise distribution in the chip with orthogonal and complanar topology of power supply feeding have been obtained. These results can be useful to estimate the trends of the EM noise in the chip and evaluate the most critical area. Further, developer can change the placing of the functional modules in the chip to increase the stability of the designed device to internal noises.

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Investigation of the internal noises in the chip with orthogonal topology of power supply feeding

Cited by 3 publications

References 3 publications

Approach to solve the reliability problem at packaging level in the matrix VLSI

Approach to solve the reliability problem at packaging level in the matrix VLSI

Frequency domain simulation of the EM internal noises in the matrix VLSI with orthogonal topology of power supply feeding

Software simulation of the noise distribution in the chip

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