Investigation of the power transistor size related to the efficiency of switching‐mode RF CMOS power amplifier

In this work, we analyze the conduction and switching losses of a supply modulator for envelope‐tracking techniques. In particular, the conduction and switching losses in the class‐D chain of the supply modulator are calculated to enhance the efficiency of the supply modulator. From the calculated results, the number of stages and fan‐out in the multiple stages of the class‐D chain are optimized. To verify the feasibility of the analyzed results, we designed a supply modulator using a 180‐nm RF CMOS process. From the measured results, we successfully prove the feasibility of the analyzed results. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:1579–1983, 2015

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“…From the previous work, the required power for switching the next stage can be calculated as follows :

P_{N - 1} = C_{N} f_{S W} V_{D D}^{2}

…”

Section: Analysis Of the Shoot‐through Current In The Class‐d Chain Omentioning

confidence: 99%

Analysis of shoot‐through current of supply modulator for envelope‐tracking techniques

Yoo

Yoon

Lee

et al. 2015

Micro & Optical Tech Letters

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“…To ensure watt-level output power, two differential pairs are designed for the power stage. The transistor size for is determined using an optimization technique proposed in an earlier work [17]. If the supply voltage directly enters through the drain node of the transistors that use additional pads and an RF choke, including external components or bonderwires, the efficiency can be enhanced.…”

Section: Design Of a Cmos Pa Using The Csc Structure With An Aprmentioning

confidence: 99%

“…Beyond a value of 2.4 V, the excessive current through the driver stages degrades the overall efficiency. Numerical analysis of the optimum necessary to improve the efficiency was provided in earlier works [16], [17]. In those earlier works, was optimized by considering the charging loss and the on-resistance loss induced by the transistors.…”

Section: Appendix Design Of Typical Cmos Pa To Determine the Transist...mentioning

confidence: 99%

“…The power consumption of the driver stage compared to that of the power stage is negligible in the high output power region. However, the power consumption of the driver stage affects the overall efficiency of the PA if the output power decreases from the maximum output power of the PA [13]- [17]. If we consider the average efficiency to extend the lifetime of the battery of a wireless mobile system, the efficiency in the low output power region needs to be improved.…”

Section: Introductionmentioning

confidence: 99%

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A Current-Shared Cascade Structure With an Auxiliary Power Regulator for Switching Mode RF Power Amplifiers

Hwang¹,

Lee²,

Park³

et al. 2014

IEEE Trans. Microwave Theory Techn.

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In this study, we propose an auxiliary power regulator (APR) for the current-shared cascade (CSC) structure of the driver stages of RF CMOS power. Although the CSC structure provides a method to reduce the power consumption at the driver stages of a differential power amplifier (PA), it is difficult to obtain optimum levels of effective supply voltage for the first and second driver stages. Additionally, the transistor sizes of the first and second driver stages of the CSC structure must be identical to ensure the proper operation of the PA. Thus, in this work, we propose an APR structure that ensures the proper operation of a PA with different transistor sizes in its first and second driver stages. To prove the feasibility of the proposed technique, we designed the PA with a CSC structure using an APR. From the measured results, we successfully verify the feasibility of the proposed structure. Additionally, we provide experimental results for a typical CMOS PA to determine the optimum supply voltage for the second driver stage.

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“…In general, this type of transformer serves as an output balun and as a key component of the output matching network in RF CMOS power amplifiers, as shown in Figure 1, assuming that the typical CMOS power amplifier is designed using a differential structure [4][5][6][7]. Although there has been much active research to improve the overall efficiency of RF CMOS power amplifiers, most studies related to CMOS power amplifiers have focused on improving the circuit structure [8][9][10][11]. Given that loss and parasitic components of the output transformer directly influence the overall efficiency and maximum output power of the CMOS power amplifier, research related to the output transformer is required [3,12,13].…”

Section: Introductionmentioning

confidence: 99%

An Asymmetric-Width Broad-Side Coupled Transformer to Reduce the Parasitic Coupling Capacitance for Cmos Power Amplifier Applications

Park¹,

Lee²,

Park³

2019

PIER M

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In this study, we propose a broad-side coupled transformer with reduced capacitance for RF CMOS power amplifier applications. The width of the secondary winding is decreased to reduce parasitic coupling capacitance. Additionally, an auxiliary primary winding is added to improve the coupling between the primary and secondary windings. To prove feasibility of the proposed transformer, we design the transformer using 180-nm RF CMOS technology. From the simulated results of a typical transformer and the proposed broad-side coupled transformer, we successfully find that the parasitic coupling capacitance of the proposed structure is reduced compared to that of a typical structure. Additionally, the auxiliary primary winding increases the maximum available gain of the proposed transformer.

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Investigation of the power transistor size related to the efficiency of switching‐mode RF CMOS power amplifier

Cited by 5 publications

References 19 publications

Analysis of shoot‐through current of supply modulator for envelope‐tracking techniques

Analysis of shoot‐through current of supply modulator for envelope‐tracking techniques

A Current-Shared Cascade Structure With an Auxiliary Power Regulator for Switching Mode RF Power Amplifiers

An Asymmetric-Width Broad-Side Coupled Transformer to Reduce the Parasitic Coupling Capacitance for Cmos Power Amplifier Applications

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