Investigation of TSV Liner Interface With Multiwell Structured TSV to Suppress Noise Propagation in Mixed-Signal 3D-IC

Kino, Hisashi; Fukusima, Takafumi; Tanaka, Tetsu

doi:10.1109/jeds.2019.2936180

Cited by 6 publications

(3 citation statements)

References 21 publications

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“…These results imply that the proposed memory device has the potential for implementing large-scale low-power SNN circuits. To enhance the performance of SNN circuits with non-volatile tunnel-FET memory, we consider that novel technologies such as heterojunctions [24], [25], two-dimensional materials [26], metal-nanodots flash memory [27], and three-dimensional integration [25], [28], are promising candidates. In the future, we plan to fabricate this SNN system with the non-volatile tunnel-FET memory developed in this study and other novel technologies.…”

Section: Discussionmentioning

confidence: 99%

Generation of STDP With Non-Volatile Tunnel-FET Memory for Large-Scale and Low-Power Spiking Neural Networks

Kino

Fukushima

Tanaka

2020

IEEE J. Electron Devices Soc.

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Spiking neural networks (SNNs) have attracted considerable attention as next-generation neural networks. As SNNs consist of devices that have spike-timing-dependent plasticity (STDP) characteristics, STDP is one of the critical characteristics we need to consider to implement an SNN. In this study, we generated the STDP of a biological synapse with non-volatile tunnel-field-effect-transistor (tunnel FET) memory that has a charge-storage layer and a tunnel FET structure. Tunnel FET is a promising structure to reduce the operation voltage owing to its steep sub-threshold slope. Therefore, the non-volatile tunnel-FET memory we propose enables the implementation of low-operation-voltage SNNs. This paper reports the I-V, programing, and both symmetric and asymmetric STDP characteristics of a non-volatile tunnel-FET memory with p-channel-MOS-like operation.

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Section: Discussionmentioning

confidence: 99%

Generation of STDP With Non-Volatile Tunnel-FET Memory for Large-Scale and Low-Power Spiking Neural Networks

Kino

Fukushima

Tanaka

2020

IEEE J. Electron Devices Soc.

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“…As shown in Fig. 2, the 3D-stacking technology [21,22,23,24] is a promising solution to address this issue. In our previous work [7,8], the sensing part transfers the photocurrent to the stimulator by Through-Silicon Via (TSV).…”

Section: Introductionmentioning

confidence: 99%

3D-stacked retinal prosthesis chip with binary image capture and edge detection functions for human visual restoration

Liang

Nakamura

et al. 2022

IEICE Electron. Express

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Retinal prosthesis is a promising treatment for vision degeneration. However, clinical experiments show that the patients can only recognize several grayscales at low resolution with electrical stimulation. This paper proposes a retinal prosthesis chip with binarization and edge detection functions to maximize the brightness difference and reduce redundant information. The binarization operation is designed as a column-parallel processing element for saving space. Moreover, the fill factor achieves 50.79% by separating the sensor and stimulator into different chips. Finally, the SPICE simulator verified the effectiveness of the proposed circuit, which achieves an FoM of 110 nW/(frame•pixel).

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“…Coupling capacitance is considered to be a key factor for signal integrity optimization. Many efforts have been made to reduce the capacitance, including low-k dielectric bilayer liner 17) and thicker dielectric layer, 18) etc. Several elaborate capacitance models have been proposed 19,20) to analytically calculate the coupling capacitance with consideration of the Metal-oxide-semiconductor effects between TSVs and the substrate.…”

Section: Introductionmentioning

confidence: 99%

Characterization of corner/edge effects of through silicon via arrays and layout optimization in 3D integrated circuits

Zhao

Sun

et al. 2021

Jpn. J. Appl. Phys.

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Signal integrity in high density through silicon via (TSV) has become a key concern in 3D integrated circuits design as its continuous scaling down. In this paper, the corner/edge effect of TSV arrays is proven to be non-neglectable and is characterized by coupling capacitance, mutual inductance, S parameter, and maximum noise respectively. The 6C static shielding method (X. Cui et al., ICEPT, 2018, p. 944) is improved by inserting ground TSVs at the array corners according to our evaluation. At last, we proposed three layout optimization rules for TSV interposer design to generate a more balanced electromagnetic shielding and to achieve better signal integrity.

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Investigation of TSV Liner Interface With Multiwell Structured TSV to Suppress Noise Propagation in Mixed-Signal 3D-IC

Cited by 6 publications

References 21 publications

Generation of STDP With Non-Volatile Tunnel-FET Memory for Large-Scale and Low-Power Spiking Neural Networks

Generation of STDP With Non-Volatile Tunnel-FET Memory for Large-Scale and Low-Power Spiking Neural Networks

3D-stacked retinal prosthesis chip with binary image capture and edge detection functions for human visual restoration

Characterization of corner/edge effects of through silicon via arrays and layout optimization in 3D integrated circuits

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