Investigation on Effect of Interface Trap Charges and Temperature in Gate Overlap Graphene Source Step Shape Double Gate Tunnel FET

Abstract

This work evaluates the electrical parameters of Gate Overlap Graphene source Step Shape Double Gate TFET (GO-GR-SSDG-TFET) with wide variation in interface trap charges (ITCs) and temperature. Here, both the positive interface charges (PITCs) and negative interface charges (NITCs) along with temperature ranges from 200-500 K on DC, RF/analog and linearity characteristics are analyzed using TCAD Sentaurus Simulator. It is observed that there is improvement (degradation) in current ratio, transconductance, gain, cut-off frequency, and delay with increase (decrease) in PITC (NITC), whereas, opposite trend is realized in terms of linearity parameters. The rise in temperature leads to degradation is subthreshold behaviour due to exponential characteristic of Shockley-Read-Hall (SRH) recombination with temperature. It is also seen that at high temperature there is degradation transconductance, device efficiency, cut-off frequency, current ratio, delay, and temperature sensitivity (ST) in the proposed TFET. Moreover, the linearity parameters are degraded with rise in temperature. Finally, a comparison table is highlighted in terms of various electrical parameters for proposed TFET with existing data.