Investigation on Single Pulse Avalanche Failure of 3.3kV planar-SiC power MOSFETs

Chen, Haonan; Wang, Jun; Dong, Ruixiao; Yao, Jiatao; Liang, Shiwei

doi:10.1109/syps59767.2023.10268224

2023 IEEE PELS Students and Young Professionals Symposium (SYPS) 2023

DOI: 10.1109/syps59767.2023.10268224

|View full text |Cite

Investigation on Single Pulse Avalanche Failure of 3.3kV planar-SiC power MOSFETs

Haonan Chen,

Jun Wang,

Ruixiao Dong

et al.

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2023

2024

Publication Types

Select...

Article2

Relationship

Self Cite0

Independent2

Authors

Journals

Cited by 2 publications

(1 citation statement)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This translates to a 1.2× higher avalanche capability for the new design.The simulated UIS waveforms for B-VDMOSFET and DPNB-VDMOSFET after failure are shown in Figure5a,b. These waveforms differ slightly from the waveforms measured in[37]. Whether the avalanche current in the device will eventually return to zero is usually used as a criterion for avalanche failure.…”

mentioning

confidence: 91%

A Two-Dimensional Computer-Aided Design Study of Unclamped Inductive Switching in an Improved 4H-SiC VDMOSFET

Nie,

Wang,

et al. 2023

Micromachines

View full text Add to dashboard Cite

Due to its high thermal conductivity, high critical breakdown electric field, and high power, the silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) has been generally used in industry. In industrial applications, a common reliability problem in SiC MOSFET is avalanche failure. For applications in an avalanche environment, an improved, vertical, double-diffused MOSFET (VDMOSFET) device has been proposed. In this article, an unclamped inductive switching (UIS) test circuit has been built using the Mixed-Mode simulator in the TCAD simulation software, and the simulation results for UIS are introduced for a proposed SiC-power VDMOSFET by using Sentaurus TCAD simulation software. The simulation results imply that the improved VDMOSFET has realized a better UIS performance compared with the conventional VDMOSFET with a buffer layer (B-VDMOSFET) in the same conditions. Meanwhile, at room temperature, the modified VDMOSFET has a smaller on-resistance (Ron,sp) than B-VDMOSFET. This study can provide a reference for SiC VDMOSFET in scenarios which have high avalanche reliability requirements.

show abstract

mentioning

confidence: 91%

A Two-Dimensional Computer-Aided Design Study of Unclamped Inductive Switching in an Improved 4H-SiC VDMOSFET

Nie,

Wang,

et al. 2023

Micromachines

View full text Add to dashboard Cite

show abstract

A Comprehensive Analysis of Unclamped-Inductive-Switching-Induced Electrical Parameter Degradations and Optimizations for 4H-SiC Trench Metal-Oxide-Semiconductor Field-Effect Transistor Structures

Liu,

Guo,

Shi

et al. 2024

Micromachines

View full text Add to dashboard Cite

This paper presents a comprehensive study on single- and repetitive-frequency UIS characteristics of 1200 V asymmetric (AT) and double trench silicon carbide (DT-SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) and their electrical degradation under electrical–thermal working conditions, investigated through experiment and simulation verification. Because their structure is different, the failure mechanisms are different. Comparatively, the gate oxide of a DT-MOSFET is more easily damaged than an AT-MOSFET because the hot carriers are injected into the oxide. The parameters’ degradation under repetitive UIS stress also requires analysis. The variations in the measured parameters are recorded to evaluate typical electrical features of device failure. Furthermore, TCAD simulation is used to reveal the electrothermal stress inside the device during avalanche. Additionally, failed devices are decapsulated to verify the location of the failure point. Finally, a new type of stepped-oxide vertical power DT MOSFET with P-type shielding and current spread layers, along with its feasible process flow, is proposed for the improvement of gate dielectric reliability.

show abstract

scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.

Contact Info

customersupport@researchsolutions.com

10624 S. Eastern Ave., Ste. A-614

Henderson, NV 89052, USA

This site is protected by reCAPTCHA and the Google Privacy Policy and Terms of Service apply.

Blog Terms and Conditions API Terms Privacy Policy Contact Cookie Preferences Do Not Sell or Share My Personal Information

Made with 💙 for researchers

Part of the Research Solutions Family.

Investigation on Single Pulse Avalanche Failure of 3.3kV planar-SiC power MOSFETs

Cited by 2 publications

References 12 publications

A Two-Dimensional Computer-Aided Design Study of Unclamped Inductive Switching in an Improved 4H-SiC VDMOSFET

A Two-Dimensional Computer-Aided Design Study of Unclamped Inductive Switching in an Improved 4H-SiC VDMOSFET

A Comprehensive Analysis of Unclamped-Inductive-Switching-Induced Electrical Parameter Degradations and Optimizations for 4H-SiC Trench Metal-Oxide-Semiconductor Field-Effect Transistor Structures

Contact Info

Product

Resources

About