Investigation on the Gate Electrode Configuration of IGZO TFTs for Improved Channel Control and Suppression of Bias-Stress Induced Instability

Abstract

This work presents an investigation on TFTs which have been fabricated with very similar process flows with the exception of the placement of the gate electrode. Bottom-gate TFTs with back-channel passivation that demonstrate good performance and resistance to aging have been realized, however bias-stress stability continues to remain a challenge. Top-gate TFTs have demonstrated improvement in the uniformity of device operation as well as bias-stress stability, and have the potential to offer an advantage in off-state performance. Double-gate TFTs take further advantage of improved electrostatics, but present additional challenges in process integration. Device operation and response to applied bias-stress of all three gate electrode configurations will be compared, with reference to TCAD simulations that utilize common bulk and interface defect models. Electrical measurements and TCAD simulations are also used to develop a hypothesis on the origin of non-ideal behavior observed on scaled devices, which can be addressed by appropriate gate electrode option.

Scalable, High-Performance Printed InOx Transistors Enabled by Ultraviolet-Annealed Printed High-k AlOx Gate Dielectrics

“…As shown below in Figure a, the linear and saturation transfer characteristics of printed TFTs on 200 nm thick AlO x dielectrics have steep turn on (subthreshold slope < 150 mV/dec) and show minimal counter-clockwise hysteresis (<50 mV). Additionally, the well-matched turn-on voltage ( V on ) for the linear and saturation regimes indicates the lack of any DIBL-like behavior . These characteristics suggest that the integration of InO x with UV-annealed AlO x is a favorable combination for producing a superior semiconductor to the dielectric interface, leading to well-behaved, stable device characteristics.…”

Channel Shape Effects on Device Instability of Amorphous Indium–Gallium–Zinc Oxide Thin Film Transistors

“…Moreover, without any degradation of electrical properties such as subthreshold swing or on–off ratio, the parallel shift of V th implies the simple charge trapping between the channel and insulator is associated with device instability. Furthermore, in most of the previous studies of the instability of a-IGZO TFTs under positive bias stress, it has been concluded that electron trapping at the interface and/or in the bulk region of the insulator is the mechanism responsible for a threshold voltage shift (∆ V th ) [ 24 , 25 , 26 , 27 , 28 , 29 , 30 , 31 , 32 ]. In this study, ambient effects were excluded for the origin of bias stress instability by existence of the passivation layer.…”

A 2D Empirical Model for On-State Operation of Scaled IGZO TFTs Exemplifying the Physical Response of TCAD Simulation

“…Additional TFTs that included different G ox thickness, anneal recipes, back-channel passivation, and a double-gate (DG) electrode configuration were also used for both TCAD and model comparisons. Details of device fabrication can be found elsewhere (5,12). Long-channel devices were initially used to suppress SCE and avoid confounding between SCE and the influence of BTS.…”