Investigation on the interface resistance of Si/GaAs heterojunctions fabricated by surface-activated bonding

Abstract

junctions fabricated by surface-activated bonding (SAB) were investigated. An amorphous layer with a thickness of 3 nm was found across the bonding interface without annealing. The current-voltage (I-V) characteristics of p +-GaAs/n +-Si, p +-Si/n +-GaAs, n +-Si/n +-GaAs, and p +-Si/p +-GaAs junctions showed excellent linearity. The interface resistance of n +-Si/n +-GaAs junctions was found to be 0.112 Ω&cm 2 , which is the smallest value observed in all the samples. The resistance decreased with increasing annealing temperature and decreased to 0.074 Ω&cm 2 after the junction annealing at 400°C. These results demonstrate that n +-Si/n +-GaAs junctions are suitable for the connection of subcells in the fabrication of tandem solar cells.

GaAs solar cell on Si substrate with good ohmic GaAs/Si interface by direct wafer bonding

“…1(c), the oxide layer was found to be amorphous. In the previously reported bonded GaAs/Si interface by a low temperature bonding [21,25], a similar interfacial layer was also observed and the thickness of an interfacial layer was around 3-5 nm. The thickness of the layer in Fig.…”

“…This resistance value is quite low compared to previously reported R interface values of the bonded GaAs/Si (0.1 Ω cm 2 from [19], nonohmic from [17,20], and 7 Â 10 À 2 Ω cm 2 from [21]). This indicated good bonding of the GaAs and Si.…”

“…The two wafers were successfully bonded without any voids, even without a high pressure and high temperature post-annealing processes. This would not only significantly reduce the processing time and thermal budget for the formation of GaAs-on-Si structures but also avoid undesirable strain by the thermal expansion mismatch, whereas the typical SAB needs a high bonding pressure [20][21][22][23][24][25]. A high-resolution cross-sectional transmission electron microscopy image and a fast Fourier transformation (FFT) image of the high-resolution TEM image are shown in Fig.…”

“…However, the processing time needed for the wafer bonding was three hours, and the two pieces were required to be pressed together during the bonding step [19]. On the other hand, recent publications have shown the feasibility of a low temperature bonding called "surface activated bonding (SAB)" with a short process time [20][21][22][23][24][25]. These results showed a better ohmic behavior of bonded III-V/Si interface than previous high temperature bondings and demonstrated a triple junction tandem cell with the III-V top cell stacked on the Si substrate.…”

Intrinsic microstructure of Si/GaAs heterointerfaces fabricated by surface-activated bonding at room temperature

“…We briefly discuss the origin of the resistance at the SABfabricated Si=GaAs interfaces. The resistance for the interfaces (∼10 −1 Ω cm 2 ), 22) as well as for GaAs=GaAs ones (∼10 1 Ω cm 2 ), 19) is higher than that for the Si=Si interfaces fabricated under a similar SAB condition (∼10 −3 Ω cm 2 ). 20) This suggests that the interface resistance would be mainly originate from the defects at the intermediate layer on the GaAs substrate.…”