Investigations and measurements of the dynamic performance of high speed ADCs

Abstract

The accuracy of ultra high speed Analog-to-Digital converters (ADCs) decreases at higher input frequencies (beyond 100 MHz) [1, 2, 3]. This is mainly due to timing mismatches, which make the comparators sample different time points of the input signal. The errors caused by the timing jitter increase at higher slew rates. Investigations concerning the origin of the aperturejitter in a 4-bit parallel ADC implemented in a 0,5 mu m GaAs FET technology were undertaken. On-chip E-beam measurements of the comparator clock distribution, implemented by a tree structure, have shown a deviation of 20 ps between the 1st and the 15th comparator of the comparator bank. A comparison with simulation results considering process variations shows similar results. The E-beam measurement of the input signal delay between the 1st and the 15th comparator shows a delay of 25 ps. To overcome these problems, a GaAs 5-bit 1 GSps ADC with on-chip Track & Hold (T & H) circuitry was developed [4]. The T & H in fron t of the quantizer samples the input signal with an optimized switch (diode bridge) providing a pseudostatic signal to the comparators. A complete DC and AC characterization of the 5-bit ADC using Histogram Test, Fast Fourier Transform Test, Sine Wave Curve Fitting Test and Beat Frequency Test up to 1.3 GHz was performed. The measurement set-up for performing all the dynamic tests consists of a 4 GHz sine wave generator, a 10 GHz pulse generator, an 8 bit wide 700 MHz, digital acquisition system for data recording, and a PC. For datarates higher than 700 MHz every second word was recorded. By using the T & H in front of the parallel ADC, 4.8 ENOB (effective number of bits) are achieved at 1 GHz input signal compared to 3.7 ENOB without T & H circuitry. A comparison of the different test methods, and results will be given