Investigations of effects of bias polarization and chemical parameters on morphology and filling capability of 130 nm damascene electroplated copper

Abstract

Through elucidating the effects of current density, cupric ion concentration, bath temperature, and air agitation on plating uniformity and filling capability of copper electroplating, the deposition of copper in an acid copper electrolyte will be illustrated to scale down to the sub-0.13 m features with uniform plating, which is required by chemical mechanical polishing in current damascene techniques. In order to achieve the defect-free filling in sub-0.13 m vias and trenches, the electrolyte must be composed of proper amounts of cupric ions, sulfuric acid, chloride ions, wetting agent, and filling promoter. The supplied current controlled at a lower current density, agitation acceded to the electroplating process were found as further keys. In the electrolyte, the filling promoter was consisted essentially of thiazole derivatives with benzyl groups and amino-group (ϪNH 2 ͒ offering sufficient inhibition on copper depositing and selective inhibition gradient. Moreover, a lower resistivity film and higher filling capability could be obtained by using periodic pulse current plating as compared with direct current plating.

Investigations of pulse current electrodeposition for damascene copper metals

“…Too low current density cannot provide significant overpotential to obtain denser deposits; however, when too much current is supplied, cupric ions are reduced too fast and Cu aggregation occurs around the protrusion on the surface under higher electric field, thus leading to deposits with rough and porous structures. 5 Figure 2͑b͒ also shows that the resistivity of those films were consistent with the trend of Fig. 2͑a͒.…”

“…As the applied current density increases in both dc and PC plating, Figure 2͑a͒ shows that the grain size became smaller due to an increase of the nucleation rate, resulting in deposits with reduced porosity and finer grains. 5 The deposition time was 5 s for both dc and PC plating in the standard electrolyte, and the frequency and the duty cycle were held at 100 Hz and 50%, respectively, in the PC plating. Too low current density cannot provide significant overpotential to obtain denser deposits; however, when too much current is supplied, cupric ions are reduced too fast and Cu aggregation occurs around the protrusion on the surface under higher electric field, thus leading to deposits with rough and porous structures.…”

“…To enhance filling capability and to reduce surface roughness of electroplated copper in multilevel interconnects, plating electrolytes usually contain proprietary additive chemistries such as brighteners and levelers. [1][2][3][4][5] For the damascene process, the superfilling phenomenon occurs when the adsorption and consumption rates of additives on the cathode are predominantly diffusion controlled. 1 For maintaining transport control of the inhibitor flux, the adsorbate must either consume into the growing film or undergo reductive desorption during metal deposition.…”

Nanoscale Electrodeposition of Copper on an AFM Tip and Its Morphological Investigations

“…In the present study, the formation of uniform copper deposits on the AFM probe could be attributed to the enhanced mass transfer of copper ions with the increase in current density. Litearture reports (Chang, 2001) describe that increase in plating current density increased the surface roughness and reduced the grain size of copper films due to an increase of plating overpotential. Several other researchers have demonstrated that the polarization overpotential increased with increasing the plating current density leading to high copper nucleation rate (Takahashi & Gross, 1999a, 2000Tean et al, 2003;Teh et al, 2001).…”

Effect of Ashing Conditions and Optimization of Nano Process Integration in Copper/Porous Low-k Nano-Interconnects

“…The use of electroplated copper showed a superfilling characteristic in advanced integrated circuits, mainly due to increased electromigration (EM) resistance. [9][10][11][12] Based on fluorinated silica glass (FSG) with a dielectric constant (k) of about 3.7, Cu metallization has been developed in logic devices of 0.13 m technology node. Due to the high resistance resulting from the fluorine reactivity with metal lines such as Al or Cu, organosilicate glass (OSG) with good resistance to oxidation has been developed as below 90 nm technology node devices with low dielectric constant below 2.9.…”