Investigations on the Negative Shift of the Threshold Voltage of Polycrystalline Silicon Thin-Film Transistors Under Positive Gate Bias Stress

Liang, Nairi; Zhang, Dongli; Wang, Mingxiang; Wang, Huaisheng; Yu, Young Moon; Qi, Dongyu

doi:10.1109/ted.2020.3041568

Cited by 4 publications

(1 citation statement)

References 17 publications

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“…[4] In addition to the electrical performance of the asfabricated poly-Si TFTs, degradation behavior and the corresponding degradation mechanisms under various kinds of bias stress should be well understood before the optimal design of poly-Si TFTs and TFT-based circuits. Stress conditions, such as positive gate bias stress, negative gate bias stress (NBS), and hot-carrier (HC) effect, could all result into degradation in TFTs' electrical characteristics, but the typical degradation phenomena obviously differ, exhibiting positive [5] and negative shift of the transfer curves [6][7][8] and decreased on-state current (I on ) with unaffected subthreshold characteristics, [9] respectively.…”

Section: Introductionmentioning

confidence: 99%

Degradation mechanisms for polycrystalline silicon thin-film transistors with a grain boundary in the channel under negative gate bias stress

Zhang¹,

Wang²,

Wang³

2022

Chinese Phys. B

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In this paper, the negative gate bias stress (NBS) reliability of n-type polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with a distinct defective grain boundary (GB) in the channel was investigated. Results showed that conventional NBS degradation with negative shift of the transfer curves is absent. The on-state current is decreased, but the subthreshold characteristics are not affected. The gate bias dependence of the drain leakage current at V ds of 5.0 V is suppressed, whereas the drain leakage current at V ds of 0.1 V exhibits obvious gate bias dependence. As confirmed via TCAD simulation, the corresponding mechanisms are proposed to be trap state generation in the GB region, positive-charge local formation in the gate oxide near the source and drain, and trap state introduction in the gate oxide.

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Section: Introductionmentioning

confidence: 99%

Degradation mechanisms for polycrystalline silicon thin-film transistors with a grain boundary in the channel under negative gate bias stress

Zhang¹,

Wang²,

Wang³

2022

Chinese Phys. B

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Investigations on the Light-Induced Degradation of P-Channel Poly-Silicon Thin Film Transistors

Zhang,

Wang,

Wang

et al. 2023

2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)

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Increased Threshold Voltage of Amorphous InGaZnO Thin-Film Transistors After Negative Bias Illumination Stress

Hong,

Zhang,

Zhang

et al. 2024

IEEE J. Electron Devices Soc.

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Degradation phenomena featured with positive shift of the on-state transfer curve are reported for the amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) under negative bias illumination stress (NBIS). Such a positive shift is absent when the gate bias or the illumination is independently applied. With the assistance of TCAD simulation, the positive shift of the transfer curve is attributed to the generation of acceptor-like trap states, which is proposed to be due to oxygen interstitials produced as a consequence of electron generation by the illumination, acceleration under the effect of negative gate bias, and breaking weakly bonded oxygen. The proposed degradation mechanism is consistent with the low frequency noise characteristics and the degradation behavior under bipolar gate bias stress of the TFTs after NBIS. The whole degradation phenomena for the a-IGZO TFT under the NBIS are then consistently explained.

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Investigations on the Negative Shift of the Threshold Voltage of Polycrystalline Silicon Thin-Film Transistors Under Positive Gate Bias Stress

Cited by 4 publications

References 17 publications

Degradation mechanisms for polycrystalline silicon thin-film transistors with a grain boundary in the channel under negative gate bias stress

Degradation mechanisms for polycrystalline silicon thin-film transistors with a grain boundary in the channel under negative gate bias stress

Investigations on the Light-Induced Degradation of P-Channel Poly-Silicon Thin Film Transistors

Increased Threshold Voltage of Amorphous InGaZnO Thin-Film Transistors After Negative Bias Illumination Stress

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