(Invited) Challenges on Surface Conditioning in 3D Device Architectures: Triple-Gate FinFETs, Gate-All-Around Lateral and Vertical Nanowire FETs

Veloso, A.; Paraschiv, Vasile; Vecchio, E.; Devriendt, K.; Li, Waikin; Simoen, Eddy; Chan, B. T.; Tao, Zheng; Rosseel, Erik; Loo, Roger; Milenin, Alexey; Kunert, Bernardette; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Dorp, Dennis van; Altamirano-Sánchez, Efraín; Brus, S.; Marien, Philippe; Fleischmann, Claudia; Melkonyan, Davit; Huynh-Bao, T.; Eneman, G.; Hellings, Geert; Sibaja-Hernandez, A.; Matagne, Philippe; Waldron, Niamh; Mocuta, D.; Collaert, N.

doi:10.1149/08002.0003ecst

Cited by 7 publications

(3 citation statements)

References 19 publications

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“…Moreover, they have advantages over FinFETs as the selector transistors in nonvolatile memory technology such as MRAM for the 3 nm node . However, the fabrication of vGAAFETs is still challenging, such as metal contamination, accurate gate-length control, the alignment of the gate with the channel, and doping strategies in channel and source/drain regions (S/D). ,− To solve the problem of metal contamination, top-down technology was introduced. , Toward the gate-related technology, in some gate-first processes, the integration of high-κ dielectrics and metal gates is difficult . The gate-last module was introduced with replaced metal gates (RMG), which provided great flexibility for the gate dielectrics and metal materials.…”

Section: Introductionmentioning

confidence: 99%

First Demonstration of Novel Vertical Gate-All-Around Field-Effect-Transistors Featured by Self-Aligned and Replaced High-κ Metal Gates

Zhu

Zhang

et al. 2021

Nano Lett.

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A novel n-type nanowire/nanosheet (NW/NS) vertical sandwich gate-all-around field-effect-transistor (nVSAFET) with self-aligned and replaced high-κ metal gates (HKMGs) is presented for the first time, aiming at a 3 nm technology node and beyond. The nVSAFETs were fabricated by an integration flow of Si/SiGe epitaxy, quasi-atomic layer etching (qALE) of SiGe selective to Si, formation of SiGe/Si core/shell NS/NW structure, building of nitride dummy gate, and replacement of the dummy gate. This fabrication method is complementary metal oxide semiconductor (CMOS)-compatible, simple, and reproducible, and NWs with a diameter of 17 nm and NSs with a thickness of 20 nm were obtained. Excellent control of short-channel-effects was presented. The device performance was also investigated and discussed. The proposed integration scheme has great potential for applications in chip manufacturing, especially with vertical channel devices.

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Section: Introductionmentioning

confidence: 99%

First Demonstration of Novel Vertical Gate-All-Around Field-Effect-Transistors Featured by Self-Aligned and Replaced High-κ Metal Gates

Zhu

Zhang

et al. 2021

Nano Lett.

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“…From 22 to 7 nm nodes, FinFETs face increasing problems, such as the short channel effect (SCE) and patterning challenges [3−7] . Stacked gate-all-around (GAA) channels with nanowires (NWs) [8−10] or nanosheets (NSs) [11] are promising structures to meet the roadmap requirements for electrostatic control, density, and performance [12,13] . A GAAFET structure allows for the design of channel width to satisfy current diversification for devices on a single wafer with a low area cost.…”

Section: Introductionmentioning

confidence: 99%

Multiple SiGe/Si layers epitaxy and SiGe selective etching for vertically stacked DRAM

Kong,

Lin,

Wang

et al. 2023

J. Semicond.

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Fifteen periods of Si/Si0.7Ge0.3 multilayers (MLs) with various SiGe thicknesses are grown on a 200 mm Si substrate using reduced pressure chemical vapor deposition (RPCVD). Several methods were utilized to characterize and analyze the ML structures. The high resolution transmission electron microscopy (HRTEM) results show that the ML structure with 20 nm Si0.7Ge0.3 features the best crystal quality and no defects are observed. Stacked Si0.7Ge0.3 ML structures etched by three different methods were carried out and compared, and the results show that they have different selectivities and morphologies. In this work, the fabrication process influences on Si/SiGe MLs are studied and there are no significant effects on the Si layers, which are the channels in lateral gate all around field effect transistor (L-GAAFET) devices. For vertically-stacked dynamic random access memory (VS-DRAM), it is necessary to consider the dislocation caused by strain accumulation and stress release after the number of stacked layers exceeds the critical thickness. These results pave the way for the manufacture of high-performance multivertical-stacked Si nanowires, nanosheet L-GAAFETs, and DRAM devices.

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“…Etching rate and micro-roughness after film strip for different films and chemicals on a 450 mm alpha single-wafer spin cleaning tool 21). …”

mentioning

confidence: 99%

Most Advanced Semiconductor Surface Cleaning : Current Problems and Future Prospects

Hattori¹

2018

Vac. Surf. Sci.

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With semiconductor-device geometry shrinking and becoming more complex, conventional aqueous cleaning/drying of semiconductor surfaces tends to collapse high-aspect-ratio nano-structures due to the surface tension of rinsing water. This is one of the most significant problems in leading-edge semiconductor manufacturing. Some current problems in the most advanced semiconductor surface cleaning and several possible solutions to overcome the shortcomings of water-based cleaning will be described and discussed with special emphasis on non-aqueous or dry wafer-surface cleaning technologies to prevent the pattern collapse problem. While semiconductor device geometry will scale down to 5-nm and below in the near future, completely different materials and device structures will be introduced in the semiconductor-device manufacturing. Larger diameter (450-mm) silicon wafers will also be employed in the future. There will be more research challenges and opportunities in developing innovative semiconductor surface cleaning and conditioning technologies for these future applications.

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(Invited) Challenges on Surface Conditioning in 3D Device Architectures: Triple-Gate FinFETs, Gate-All-Around Lateral and Vertical Nanowire FETs

Cited by 7 publications

References 19 publications

First Demonstration of Novel Vertical Gate-All-Around Field-Effect-Transistors Featured by Self-Aligned and Replaced High-κ Metal Gates

First Demonstration of Novel Vertical Gate-All-Around Field-Effect-Transistors Featured by Self-Aligned and Replaced High-κ Metal Gates

Multiple SiGe/Si layers epitaxy and SiGe selective etching for vertically stacked DRAM

Most Advanced Semiconductor Surface Cleaning : Current Problems and Future Prospects

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