(Invited) Gate Stacks for Silicon, Silicon Germanium, and III-V Channel MOSFETs

Abstract

High-k gate dielectrics such as HfO 2 and metal gates such as TiN have been deployed across a wide range of silicon-based CMOS logic products. In some gate-first technologies, SiGe channels (cSiGe) have been implemented simultaneously for threshold voltage control in p-channel metal-oxide-semiconductor fieldeffect transistors (pMOSFET). Herein, we review aspects related to the impact of high-k/channel interfacial layers on Si, SiGe, and III-V gate stack quality and device performance. First, we review remote oxygen scavenging approaches for interfacial SiO 2 thinning in HfO 2 /Si nFET and HfO 2 /cSiGe pFET devices. We show that they allow equivalent oxide thickness (EOT) to be reduced to 0.4-0.5 nm, and we discuss device performance and reliability tradeoffs that may limit continued EOT scaling. For later technology nodes, high-carrier-mobility III-V semiconductors channels such as InGaAs are under consideration. We summarize three high-k/InGaAs channel interface approaches: Direct high-k deposition, Si capping, and InP capping.

(Invited) TmSiO as a CMOS-Compatible High-k Dielectric

“…Since the 45 nm node (1), scaling of logic transistors in complementary metal-oxidesemiconductor (CMOS) technology has relied on the implementation of high-k/metal gates in place of the conventional SiON/poly-Si gates, enabling low equivalent oxide thickness (EOT) while keeping the gate leakage current density within specifications (2)(3)(4)(5). State-of-the-art high-k/metal gate CMOS technology employs Hf-based oxides (typically HfO2) as the "bulk" high-k oxide layer, whose thickness is designed as a tradeoff between EOT scaling and gate current control.…”