Invited paper: Using OpenCL to evaluate the efficiency of CPUS, GPUS and FPGAS for information filtering

Chen, Doris; Singh, Deshanand P.

doi:10.1109/fpl.2012.6339171

Cited by 39 publications

(15 citation statements)

References 4 publications

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“…Two primary FPGA vendors, Intel and Xilinx, provide developers with their high-level tools. Intel released several high-level development tools such as high-level synthesis (HLS) compiler, which supports C++ based development, and FPGA SDK for FPGA, which supports OpenCL [3], [4] based development. Xilinx provides two main tools: 1) highlevel synthesis of C/C++ and SystemC and 2) SDAccel that supports OpenCL.…”

Section: High-level Synthesismentioning

confidence: 99%

Harmonic-Summing Module of SKA on FPGA—Optimizing the Irregular Memory Accesses

Wang

Prabu

Sinnen

2019

IEEE Trans. VLSI Syst.

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The Square Kilometre Array (SKA), which will be the world's largest radio telescope, will enhance and boost a large number of science projects, including the search for pulsars. The frequency domain acceleration search is an efficient approach to search for binary pulsars. A significant part of it is the harmonic-summing module, which is the research subject of this paper. Most of the operations in the harmonic-summing module are relatively cheap operations for FPGAs. The main challenge is the large number of point accesses to off-chip memory which are not consecutive but irregular. Although harmonicsumming alone might not be targeted for FPGA acceleration, it is a part of the pulsar search pipeline that contains many other compute-intensive modules, which are efficiently executed on FPGA. Hence having the harmonic-summing also on the FPGA will avoid off-board communication, which could destroy other acceleration benefits. Two types of harmonic-summing approaches are investigated in this paper: 1) storing intermediate data in off-chip memory and 2) processing the input signals directly without storing. For the second type, two approaches of caching data are proposed and evaluated: 1) preloading points that are frequently touched 2) preloading all necessary points that are used to generate a chunk of output points. OpenCL is adopted to implement the proposed approaches. In an extensive experimental evaluation, the same OpenCL kernel codes are evaluated on FPGA boards and GPU cards. Regarding the proposed preloading methods, preloading all necessary points method while reordering the input signals is faster than all the other methods. While in raw performance a single FPGA board cannot compete with a GPU, in terms of energy dissipation, GPU costs up to 2.6x times more energy than that of FPGAs in executing the same NDRange kernels.

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Section: High-level Synthesismentioning

confidence: 99%

Harmonic-Summing Module of SKA on FPGA—Optimizing the Irregular Memory Accesses

Wang

Prabu

Sinnen

2019

IEEE Trans. VLSI Syst.

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“…In [5], the authors also developed a multi-FPGA converted bag of words system in which performance of the system yielded a tenfold speedup when combined with a conventional CPU and excellent cost-performance as well as energy consumed for the calculation. Similarly in [6], the authors assume that documents have been converted to the bag-ofwords format and focus only on the document scoring portion of the application.…”

Section: Related Workmentioning

confidence: 99%

“…When it is required to refer to the profile, the rest bits of the hit word are compared with the rest bits of the profile then if they are matched, the weight bits of this element is accumulated to the score. 6. The final result of classification will be made using naïve Bayesian classifier.…”

Section: Document Classification Sytemsmentioning

confidence: 99%

Document classification systems in heterogeneous computing environments

Nasiri

Colangelo

Segal

et al. 2016

2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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Abstract-Datacenter workloads demand high throughput, low cost and power efficient solutions. In most data centers the operating costs dominates the infrastructure cost. The ever growing amounts of data and the critical need for higher throughput, more energy efficient document classification solutions motivated us to investigate alternatives to the traditional homogeneous CPU based implementations of document classification systems. Several heterogeneous systems were investigated in the past where CPUs were combined with GPUs and FPGAs as system accelerators. The increasing complexity of FPGAs made them an interesting device in the heterogeneous computing environments and on the other hand difficult to program using Hardware Description languages. We explore the trade-offs when using high level synthesis and low level synthesis when programming FPGAs. Using low level synthesis results in less hardware resource usage on FPGAs and also offers the higher throughput compared to using HLS tool. While using HLS tool different heterogeneous computing devices such as multicore CPU and GPU targeted. Through our implementation experience and empirical results for data centric applications, we conclude that we can achieve power efficient results for these set of applications by either using low level synthesis or high level synthesis for programming FPGAs.

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“…Unlike the OpenCL compiler for CPUs and GPUs, where parallel threads are executed on different cores, AOC transforms kernel functions into deeply pipelined hardware circuits to achieve parallelism. AOC uses a CLANG front-end to parse OpenCL extensions and intrinsics to produce unoptimized LLVM IR [31]. The middle-end performs optimization with about 150 compiler passes such as loop fusion, auto vectorization, and branch elimination.…”

Section: B Altera Openclmentioning

confidence: 99%

“…Finally the generated kernel is loaded onto an Altera FPGA using an OpenCL compatible hardware image. Various applications using OpenCL to program FPGA accelerators have been demonstrated, such as information filtering [31], Monte Carlo simulation [30], finite difference [32], particle simulations [32], and video compression [33].…”

Section: B Altera Openclmentioning

confidence: 99%

High-Level Language Tools for Reconfigurable Computing

Windh

Halstead

et al. 2015

Proc. IEEE

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| In the past decade or so we have witnessed a steadily increasing interest in FPGAs as hardware accelerators:they provide an excellent mid-point between the reprogrammability of software devices (CPUs, DSPs, and GPUs) and the performance and low energy consumption of ASICs. However, the programmability of FPGA-based accelerators remains one of the biggest obstacles to their wider adoption. Developing FPGA programs requires extensive familiarity with hardware design and experience with a tedious and complex tool chain.

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Invited paper: Using OpenCL to evaluate the efficiency of CPUS, GPUS and FPGAS for information filtering

Cited by 39 publications

References 4 publications

Harmonic-Summing Module of SKA on FPGA—Optimizing the Irregular Memory Accesses

Harmonic-Summing Module of SKA on FPGA—Optimizing the Irregular Memory Accesses

Document classification systems in heterogeneous computing environments

High-Level Language Tools for Reconfigurable Computing

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