(Invited) Past, Present, and Future of High-k/Metal Gate Technologies

Iwai, Hiroshi

doi:10.1149/08001.0003ecst

Cited by 2 publications

(3 citation statements)

References 22 publications

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“…These systems can be a more extreme test of the calculations of band gap and band offsets. Table gives the calculated band gaps, electron affinities, and ionization potentials of such oxides from SX and compares them to the experimental values from compilations of Hosono, Klein, , Iwai, Greiner, and Robertson …”

Section: Resultsmentioning

confidence: 99%

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Band Offset Models of Three-Dimensionally Bonded Semiconductors and Insulators

Guo

Clark

et al. 2019

J. Phys. Chem. C

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The band offsets at a heterojunction lies between two limits, those given by the electron affinity rule and the matching of the charge neutrality levels (CNLs) or branch point energies. It is shown that it has been difficult to compare these cases because most experimental and theoretical tests require a lattice-matching across the heterojunction, and most semiconductors with the same lattice constant have similar average band energies referenced to the vacuum level. A second point is that the CNL when referenced to the vacuum level varies surprisingly weakly with the midgap energy referenced to the vacuum level. A calculation of band offsets for larger lattice mismatch heterojunctions provides a strong test, whose result is found to favour the CNL matching model. This result is important for the majority of practical device heterojunctions, where there is no match due to poly-crystallinity or other effects. For other cases whether the device consists of molecules, the electron affinity rule holds.

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Section: Resultsmentioning

confidence: 99%

“…Calculated GGA and SX values of ionization potential vs their experimental values − for some oxides.…”

Section: Resultsmentioning

confidence: 99%

Band Offset Models of Three-Dimensionally Bonded Semiconductors and Insulators

Guo

Clark

et al. 2019

J. Phys. Chem. C

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“…Threshold voltage (V T ) control is vital to realize targets for both low power and high performance in SoC (system-on-chip) applications. With the CMOS shrinking into 5 nm technology node, the multi-V T modulation needs more concern about the band-edge work function in the RMG (replacement metal gate) scheme with all last high-k metal gate, [1][2][3] which band-edge work function is very desired to realize the target of CMOS low power applications. With the emerging FinFET and GAA NWFET devices scaling into the nanoscale beyond 5 nm technology node, the conventional channel doping need overcome the serious random doping fluctuation, 4 and the strong quantum confinement of intrinsic channel properties can ruin the V T target.…”

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confidence: 99%

Novel Band-Edge Work Function Performance Modulation via NPT with PMOS^1st/NMOS^1st Laminated Stack for PMOS Low Power Target

Yao¹,

Wu²,

Tian³

2020

ECS J. Solid State Sci. Technol.

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In this paper, the band-edge work function performance is systematically investigated and modulated via novel nitrogen plasma treatment (NPT) with the advanced PMOS 1st (TiN/TiN/TiAlC) and NMOS 1st (TiN/TiN) laminated stacks for the fabricated PMOS capacitors. The basic multi-V T performance is strongly modulated by controlling NPT process. 1) Flatband voltage (V FB ) shifts towards band edge are obtained as +120 mV (undiluted), +430 mV (diluted) for PMOS 1st and +80 mV (undiluted), +210 mV (diluted) for NMOS 1st . 2) By manipulating the NPT process from undiluted and diluted case, it can provide significant high bandedge effective work function ranging from 4.89 eV (undiluted) to 5.21 eV (diluted) for PMOS 1st and 5.22 eV (undiluted) to 5.35 eV (diluted) for NMOS 1st laminated stack, respectively. 3) NPT diluted with hydrogen is observed to maintain ultralow bulk trap density (1.11 × 10 11 cm −2 for PMOS 1st and nearly zero for NMOS 1st ) and interface trap density (3.34 × 10 11 eV −1 cm −2 for PMOS 1st and 6.45 × 10 11 eV −1 cm −2 for NMOS 1st ). The significant band-edge work function modulation and very low bulk and interface trap density demonstrate the novel NPT with PMOS 1st /NMOS 1st laminated stack is very promising to achieve the target of PMOS low-power application in the further technology node.

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(Invited) Past, Present, and Future of High-k/Metal Gate Technologies

Cited by 2 publications

References 22 publications

Band Offset Models of Three-Dimensionally Bonded Semiconductors and Insulators

Band Offset Models of Three-Dimensionally Bonded Semiconductors and Insulators

Novel Band-Edge Work Function Performance Modulation via NPT with PMOS^1st/NMOS^1st Laminated Stack for PMOS Low Power Target

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(Invited) Past, Present, and Future of High-k/Metal Gate Technologies

Cited by 2 publications

References 22 publications

Band Offset Models of Three-Dimensionally Bonded Semiconductors and Insulators

Band Offset Models of Three-Dimensionally Bonded Semiconductors and Insulators

Novel Band-Edge Work Function Performance Modulation via NPT with PMOS1st/NMOS1st Laminated Stack for PMOS Low Power Target

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Product

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Novel Band-Edge Work Function Performance Modulation via NPT with PMOS^1st/NMOS^1st Laminated Stack for PMOS Low Power Target