(Invited) Replacement Metal Gate/High-k Last Technology for Aggressively Scaled Planar and FinFET-Based Devices

Abstract

This work reports on aggressively scaled replacement metal gate, high-k last (RMG-HKL) planar and FinFET-based devices using a novel effective work function (EWF) engineering approach which relies on controlled diffusion mechanisms in the gate stack and enables wide VT modulation [>500 mV ΔVT in narrow-fin (WFin≥5 nm), triple-gate FinFETs], with no EOT nor JG penalty, improved mobility and reliability, excellent mismatch performance, up to ~6.3× reduced noise, and minimized parasitic gate resistance. Additionally, we present a thorough evaluation of the impact of post high-k deposition thermal (PDA) and plasma (SF6) treatments for planar vs. FinFET devices with different Si crystal orientations, providing a deeper insight into underlying degradation mechanisms. SF6 enables improved mobility and reduced interface trapped charge density (Nit), helping to mitigate the impact of fin patterning and fin sidewall crystal orientations, while allowing a simplified dual-EWF metal CMOS scheme suitable for both device architectures. PDA results in substantially improved reliability behavior due to bulk defects reduction.

(Invited) Gate-All-Around Transistors Based on Vertically Stacked Si Nanowires

“…Another option is the integration of different work-function metals for N-and P-type Si NWFETs. We have tested this approach experimentally based on an integration scheme that was originally developed for planar devices and FinFETs (13,14). The process flow is illustrated in the schematics in Fig.…”

Low Frequency Noise Analysis of Impact of Metal Gate Processing on the Gate Oxide Stack Quality

“…31 Impact of RMG processing.-Implementation of a HKMG has become standard for state-of-the-art FinFET technologies. 32 Moreover, so-called high-κ-last or RMG integration schemes offer a wider process window for the deposition of metal-oxide cap layers to tune the effective work function and, hence, the threshold voltage. 33,34 This implies that a dummy amorphous or polysilicon gate and gate oxide need to be removed first, before fabricating the final HKMG stack.…”

“…In order to enable the deposition of a good quality gate dielectric, effective pre-cleaning of the silicon surface is of vital importance. 32,33 Different types of pre-cleaning can be considered, 35 including standard diluted HF cleaning, a remote plasma (RP) cleaning in NF 3 /NH 3 called siconi 36 or a combination of the two. This was followed by an in situ O 3 oxidation to form an interfacial SiO 2 layer (IL-SiO 2 ).…”

Fabrication of a nano-scaled tri-gate field effect transistor using the step-down patterning and dummy gate processes

“…Lastly, the metallization part has Ni-silicide for the Ohmic contact formation and Al metal formation for the contact pad open area. The entire process scheme was based on the gate-last [7] integration scheme, which is characterized by the deposition of the HKMG stack after the high temperature dopant activation annealing. Each process will be described with a detailed explanation in the following subsections.…”