IPA in the loop: Control design for throughput regulation in computer processors

Abstract

A new technique for performance regulation in event-driven systems, recently proposed by the authors, consists of an adaptive-gain integral control. The gain is adjusted in the control loop by a real-time estimation of the derivative of the plant-function with respect to the control input. This estimation is carried out by Infinitesimal Perturbation Analysis (IPA). The main motivation comes from applications to throughput regulation in computer processors, where to-date, testing and assessment of the proposed control technique has been assessed by simulation. The purpose of this paper is to report on its implementation on a machine, namely an Intel Haswell microprocessor, and compare its performance to that obtained from cycle-level, full system simulation environment. The intrinsic contribution of the paper to the Workshop on Discrete Event System is in describing the process of taking an IPA-based design and simulation to a concrete implementation, thereby providing a bridge between theory and applications.

Power regulation in high performance multicore processors

“…The plant is modelled as a discrete event dynamic system controlled by the processor's clock rate (frequency), whose output is the average instruction-throughput measured over short time frames. The technique was verified by both simulation [19], [20] and implementation on a Haswell machine [22]. In simulation the derivative term…”

“…Its performance was tested via simulation on instruction-throughput regulation [19], [20], then on throughput of abstract Discrete Event Dynamic Systems (DEDS) such as queues, Petri nets and transportation networks [21]. Lately the controller has been implemented on Intel's fourthgeneration micro-architecture, Haswell [22], where it was tested on instruction-throughput regulation.…”

Performance regulation and tracking via lookahead simulation: Preliminary results and validation

“…The resulting tracking (regulation) algorithm consists of a recursive application of Eq. ( 2), and we note that it comprises an implementation of the Newton-Raphson method for solving the algebraic equation g(u) = r. In [2], [4], [5] the use of this variable gain integrator was argued to be competitive with extant techniques for controlling power and instruction-throughput in multicore computer processors despite its simple form. An analysis in a general setting of nonlinear, memoryless systems was carried out in [6].…”

“…These applications include the regulation of power and instruction throughput by the processor's clock frequency. The rationale behind the choice of such a control architecture, as well as results of simulations on industry benchmark programs, and implementations on Intel's Haswell microarchitecture[3], can be found in[2],[4],[5].…”