2015
DOI: 10.1109/memc.2015.7407188
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IR-drop modeling and reduction for high-performance printed circuit boards

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Cited by 13 publications
(6 citation statements)
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“…In this demonstration, Port u is not used for the sake of simplicity. The positions of the other ports (x q1 , y q1 ), (x q2 , y q2 ), (x r1 , y r1 ), and (x r2 , y r2 ) are (5,4), (20,22), (20, 10.9), (24,12), and (24 mm, 0.9 mm), respectively. The power integrity characteristics of the PDN segmented by the DGS-EBG structure are analyzed using a self-impedance (Z 11 ).…”
Section: Resultsmentioning
confidence: 99%
See 1 more Smart Citation
“…In this demonstration, Port u is not used for the sake of simplicity. The positions of the other ports (x q1 , y q1 ), (x q2 , y q2 ), (x r1 , y r1 ), and (x r2 , y r2 ) are (5,4), (20,22), (20, 10.9), (24,12), and (24 mm, 0.9 mm), respectively. The power integrity characteristics of the PDN segmented by the DGS-EBG structure are analyzed using a self-impedance (Z 11 ).…”
Section: Resultsmentioning
confidence: 99%
“…As show in Figure 1a, the DGS-EBG array configures in various ways to optimize its performance considering power/ground noise isolation, design flexibility, and current-resistance (IR) drop problem. The IR drop problem induces from the narrow branches of the DGS-EBG structure, and the DGS-EBG structure should be cautiously designed considering this limitation [24]. The size of the DGS-EBG array can be defined as the number of DGS-EBG structures and the number of unit cells in a single DGS-EBG structure.…”
Section: Introductionmentioning
confidence: 99%
“…To establish the matrix equation in the k-th sudomain, the DG test is applied to (1), which leads to the following equation:…”
Section: A Formulation Of Electrostatic Potential Equation By Rtc-dgmentioning
confidence: 99%
“…The reliability problems are becoming more serious with the continuous decreasing DC operation voltage, the increasing integration density, and the ever-shrinking feature sizes. Among them, DC IR-Drop [1] is a major issue in the power integrity (PI) problem, which would bring significant challenges to the design of the power distribution networks (PDN) of integrated circuits (IC) and printed circuit broads (PCB) [2]. In addition, Joule heating resulted thermal effects could be considerable with the shrinking scale of vias and traces, which would have serious impact on the resistivity of the conductors of PDNs.…”
Section: Introductionmentioning
confidence: 99%
“…One of the most critical steps that hamper PCB design development is the generation of a power plane [2], which aims to configure the various metal planes' layout on a PCB. Although there has been significant development in automatic solvers for the critical objectives of PCB design related to power plane generation such as IR-drop solver [3,4,5], power integrity solver [6,7], and signal integrity [8,9,10], the generation of power plane itself still relies on the manual effort of electronics designers. Thus, automatic power plane generation is needed to address an unmet need in PCB design.…”
Section: Introductionmentioning
confidence: 99%