IR-level annotation strategy dealing with aggressive loop optimizations for performance estimation in native simulation

Matoussi, Omayma; Pétrot, Frédéric

doi:10.1145/3125502.3125550

Cited by 1 publication

(2 citation statements)

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“…To do so, several techniques were proposed, depending on the type of code that was to be analyzed and annotated. These techniques can be categorized [4] into binary (assembly) level simulation (BLS), IR-level simulation (IRLS) and source-level simulation (SLS), in terms of functional representation levels.…”

Section: State Of the Artmentioning

confidence: 99%

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Accelerating Host-Compiled Simulation by Modifying IR Code: Industrial application in the spatial domain

Posadas

Villar

Sánchez‐Renedo

2019

2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS)

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Space applications rely on long and complex design processes, as they must deal with strict non-functional requirements such as criticality, timeliness, reliability and safety. The huge number of analysis and evaluations performed requires powerful simulations technologies combining high simulation speed and accuracy. Host-compiled simulation is a powerful approach to achieve fast, timed simulation of software running in complex embedded systems. However, in the general term, there is still the need of improving the speed and accuracy of these solutions, and there is a lack of host-compiled approaches oriented to space applications. To solve the first point, this paper presents an alternative that modifies the standard solution of adding the modeling of the cross-compiled control flow in the host computer by modifying the compiler's intermediate representation. That way, the host binary naturally follows the cross-compiled binary flow, avoiding a separate modeling, and improving simulation speed while maintaining accuracy. Additionally, the paper focuses on LEON processor, commonly used by the European Space Agency (ESA).

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Section: State Of the Artmentioning

confidence: 99%

“…Similar alternatives have been proposed using IR level. To address the mapping problems found in early SLS work, in [4] the compiler is modified to add timing information into the Intermediate Representation (IR). However, modifying the compiler takes a lot of effort.…”

Section: State Of the Artmentioning

confidence: 99%