Iris Matching Step Implementation in FPGA

Abstract

Iris recognition system is broadly being utilized as it has distinctive patterns that gives it a powerful strategy to distinguish between persons for identification purposes. However, this system in this implementation requires large memory capacity and high computation time. These factors make us in a challenge to find a way to run this algorithm in a hardware platform. The hardware implementation features reduce the execution time by exploiting the parallelism and pipeline. The present work addresses this issue when reducing execution time by implementing the matching step using hamming distance algorithm on the target device FPGA KINTEX 7 using Xilinx system generator. The obtained result demonstrates that the execution time has been accelerated to 1.32 ns, which is almost at least four times faster than existing works