Is there a need for on-chip photonic integration for large data warehouse switches

Abstract

Over the past 18-months VCSEL based optical engines have been integrated into package of largescale HPC routers, moderate size Ethernet switches, and even FPGA's. Competing solutions based on Silicon Photonics (SiP) are emerging and targeting similar application space but with better integration path through the use of TSV (Through Silicon Via) stack dies. Integrating either VCSEL or SiP based optical engines into complex IC package that operate at high temperatures and require high reliability is not trivial, and one should ask what is the technical or the economic advantage before embarking on such a drastic architectural change. We are currently investigating the extend to which scenarios on-chip photonic integration into large-scale data warehouse switches have clear power and/or bandwidth advantages over using traditional electrical I/O. 1.0 Introduction: The need for optical interconnect for HPC applications was clearly demonstrated in case of POWER7 server [1], where 28 VCSEL based µPOD optical engines each having 12 lanes were placed on the POWER7 Router Module. The POWER7 Router Module with each lane operating at 10 Gb/s had an aggregate BW of 2.68 Tb/s excluding 8b/10B overhead. More recently, VCSEL based optical engine integrated at wafer level have been demonstrated called "Holey Optochip" with a potential to overcome substrate size and congestion, reduce foot print, and power [2]. The 10 GbE MMF link reach based on OM3 (2000 MHz.km) fiber is 300 m, but the 100 GbE link reach based on 4x25.78 GBd signaling expected to be ~70 m on OM3 and ~100 m on OM4 (4700 MHz.km) [3]. These MMF fiber reaches are adequate to meet HPC application, but does not meet reach requirements of large data warehouses requiring at least 500m.Currently large data warehouse switches front panel bandwidth-density is being limited by the front panel pluggable module at 1.44 TB/s assuming 36 ports of QSFP+ each operating at 40 GbE. On board optics would solve the front panel bandwidth-density, but somewhere in the 3-4 Tb/s the switch ASIC package will limit bandwidth for reasonable package/PCB constructions. Unlike HPC applications, these massive data centers require a minimum fiber reach of 500 m, which is well beyond the reach of any MMF fibers at 25.78 GBd. A single mode solution based on silicon photonics (SiP) MCM or TSV has the potential to not only meet the reach objective but also the cost and power targets [4].

Advances in silicon photonics segmented electrode Mach-Zehnder modulators and peaking enhanced resonant devices

“…Ongoing growth of cloud computing is creating significant challenges for interconnect systems in data centers and high performance computing systems mainly in terms of data-rate, power consumption, size and cost [1]. Emerging short range interconnect solutions are required to feature reduced power consumption and to be more cost efficient while supporting higher data rates.…”

Silicon photonics WDM transmitter with single section semiconductor mode-locked laser

“…With growing data center dimensions, a need for longer reach data center interconnects has been identified [4,5], making a transition toward SMF-based solutions attractive despite more stringent alignment tolerances during assembly. With increasing channel count, e.g., with the C-Form-Factor Pluggable (CFP) roadmap including form factors with up to 16 channels and increasing link distances, solutions relying on WDM rather than on parallel optics (with multiple fibers) are also becoming more effective despite the additional complexity associated with the implementation of a WDM system.…”

SDN enabled flexible optical data center network with dynamic bandwidth allocation based on photonic integrated wavelength selective switch

“…The proliferation of these applications increases DC traffic on a steep growth reaching 25 percent annually [3,4]. However, the current electrical switches based intra-DC interconnections are facing technical challenges because the implementation of high-bandwidth electrical switches is limited by the ASIC I/O bandwidth as the result of the scaling issue of ball grid array (BGA) package [5,6]. Stacking the ASIC boards in a multi-tier structure could increase the switching bandwidth but at the expenses of extra latency and costly complex interconnections, leading to high cost and power consumption switching architectures.…”