Is there an impact of threading dislocations on the characteristics of devices fabricated in strained‐Ge substrates?

Simoen, Eddy; Brouwers, Gijs; Yang, Rui; Eneman, G.; González, Mireia Bargalló; Leys, F.; Jaeger, B. De; Mitard, J.; Brunco, D.P.; Souriau, Laurent; Cody, N. W.; Thomas, S.G.; Lajaunie, Luc; David, Marie‐Laure; Meuris, Marc

doi:10.1002/pssc.200881446

Cited by 27 publications

(21 citation statements)

References 25 publications

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“…6 illustrates that better electrical characteristics have been obtained for the highest pre-epi bake step. 7 This is true not only for the on-current ͑hole mobility͒, but also for the off-state current, where the drain-bulk leakage current of Fig. 6 is part of.…”

Section: R2mentioning

confidence: 95%

“…4b͒ and is barely affected by annealing. 7 The strain in the as-grown s-Ge layers is in the range of 0.9%, as measured by high resolution X-ray diffraction ͑HR-XRD͒ ͑Fig. 5͒.…”

Section: Thin Strained Epitaxial Ge Layersmentioning

confidence: 99%

“…4 did not result in a higher on-current or mobility compared with reference devices fabricated in the thick Ge-on-Si layers described in the previous part. 6,8 The junction leakage current was much higher due to the higher TDD 7,24 but improved for a higher pre-epi bake temperature. At the same time, however, no clear reduction in the TDD was found, which is in line with the data in Fig.…”

Section: R2mentioning

confidence: 99%

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Extended-Defect Aspects of Ge-on-Si Materials and Devices

Simoen

Eneman

Wang

et al. 2010

J. Electrochem. Soc.

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Extended-defect aspects of state-of-the-art Ge-on-Si materials and devices are discussed with an emphasis on the impact of postgrowth thermal budget on the structural and electrical epilayer characteristics. The observations on the annealed thick and thin epitaxial layers on Si can be explained based on a thermodynamic model for the minimum density of threading dislocations ͑TDs͒. For the present processing conditions, the leakage current of Ge complementary metal oxide semiconductor compatible p + n junctions becomes independent of the TD density at about 10 7 cm −2 . © 2009 The Electrochemical Society. ͓DOI: 10.1149/1.3267514͔ All rights reserved. Defect engineering is a common practice in silicon-based integrated circuit and solar cell technology and has been extensively investigated during the past 2 decades, leading to its successful implementation in manufacturing lines. In addition, for sub-45 nm technologies, strain engineering is required to boost the device performance in agreement with the International Technology Roadmap for Semiconductors. In recent years, strong research efforts have also been focusing on the use of Ge-based channels for the sub-22 nm complementary metal oxide semiconductor ͑CMOS͒ node, 1 whereby epitaxial Ge-on-Si has a very strong potential. This also opens the door to achieve a full monolithic integration of Ge and III-V materials on a silicon substrate, leading to system-on-chip applications. The main challenge of the epitaxial deposition of Ge on Si is the 4% lattice mismatch and the difference in thermal expansion coefficient, which readily leads to the buildup of mechanical stress and, subsequently, its relaxation by the generation of misfit and threading dislocations ͑TDs͒.2,3 Therefore, the control of misfit and TDs during both substrate preparation and device processing is a must to arrive at a good-yielding, high performing technology. The aim of this paper is to summarize our recent developments in Geon-Si materials and devices and to address the remaining challenges. An extensive overview of the foregoing work can be found in Chap. 4 of Ref. 4.The focus in this work is on the defect formation and control during the fabrication of Ge virtual substrates on silicon by chemical vapor deposition. Hereby, several approaches can be followed 2-4 to optimize the threading dislocation density ͑TDD͒ either by the use of a relaxed SiGe-graded buffer layer or by the direct deposition of a thick Ge epitaxial layer on silicon. Three different cases are considered, whereby the impact of a postgrowth ͑PG͒ anneal on the TDD is highlighted, and the impact on the electrical device performance is mainly evaluated through the leakage current of p + n junctions fabricated in these layers. The procedures to separate the area from the perimeter leakage current have been outlined previously. 5,6 It is demonstrated that a PG anneal or thermal budget may have both beneficial and detrimental effects, depending on the application and type of layer. For a relaxed virtual Ge substrate, the PG anneali...

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Section: R2mentioning

confidence: 95%

“…4b͒ and is barely affected by annealing. 7 The strain in the as-grown s-Ge layers is in the range of 0.9%, as measured by high resolution X-ray diffraction ͑HR-XRD͒ ͑Fig. 5͒.…”

Section: Thin Strained Epitaxial Ge Layersmentioning

confidence: 99%

Section: R2mentioning

confidence: 99%

See 1 more Smart Citation

Extended-Defect Aspects of Ge-on-Si Materials and Devices

Simoen

Eneman

Wang

et al. 2010

J. Electrochem. Soc.

View full text Add to dashboard Cite

show abstract

“…This yields a value of a few 10 9 cm À 2 for a 100 nm epilayer. Previous investigations of Ge pMOSFET parameters have shown that a threading dislocation density in the range above 10 9 cm À 2 is required to affect the threshold voltage and the long-channel mobility [61,69], while as shown in Fig. 5, the drain-substrate diode leakage is sensitive to lower threading defect densities.…”

Section: Defect Aspects In Ge-on-si and Geoimentioning

confidence: 96%

“…5. This can be explained by the fact that in the first instance the diode leakage increases with the TDD [60,61]. In addition, it has been found that the one decade lower threading dislocation density in sGe layers also yields a lower excess GenerationRecombination (GR) noise in weak inversion transistor operation [62].…”

Section: Defect Aspects In Ge-on-si and Geoimentioning

confidence: 99%