ISFET Array Readout System with Integrated 12 bit A/D Conversion for Lab-on-Chip Applications

Hernández, Humberto Escalante; Pontes, Diego Augusto; Martins, Tarciso A.; Reyes, David; Noije, Wilhelmus Van

doi:10.1109/lascas51355.2021.9459168

Cited by 1 publication

(1 citation statement)

References 11 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…DACs híbridos, resistivo-capacitivo (RC) [23,24], ou MOSFET-capacitivo (MOS-CAP) [25]. Dessa forma, além de reduzir a área total ocupada, essas estruturas permitem ter um tempo de estabilização para o DAC maior e um menor consumo de energia do conversor.…”

Section: P/fs [Pj]unclassified

Projeto de um conversor analógico-digital para um receptor UWB aplicado na detecção de câncer de mama em tecnologia CMOS.

Gonzalez¹

View full text Add to dashboard Cite

This work presents the design of an 11 bits, 20-MS/s, Analog-to-Digital Converter (ADC) for an ultra-wideband (UWB) receiver applied in breast cancer detection in 180 nm CMOS technology.The architecture taken from the literature is known as successive approximation register (SAR). This architecture was selected because it is more efficient in energy terms compared to other architectures in order to achieve the design target of this project: a 20-MS/s ADC with a SNDR higher than 62 dB. A differential architecture was chosen to achieve a better common-mode disturbance rejection. The prototype ADC comprises a sample and hold circuit, a capacitive digital-to-analog converter (DAC), a dynamic comparator, and the logic control circuit which implements the SAR algorithm. Merged capacitor switching procedure was implemented, therefore, the differential DAC capacitor network serves both to a top-plate sampling of the input signal and subtracts the reference in the conversion process. Furthermore, the 11 bit ADC takes advantage of using 10 bit DACs, saving power and area. An asynchronous operation was selected to eliminate the need for an external high-frequency clock. To improve the linearity, a delay cell inside the asynchronous clock generator is implemented, allowing a larger settling time for the capacitive DAC.The designed ADC occupies 0.1 mm 2 and post-layout simulation results show that it achieves an ENOB of 10.73 bit at a sampling rate of 20 MS/s and an input tone at Nyquist rate. The power consumption is 2.89 mW at 1.8 V supply, thus achieving the figure of merits of Schreier (FoM S ) and Walden (FoM W ), 162 dB and 84 fJ/conv.-step, respectively. At 20-MS/s, 1,8-V, the DNL is +0,32/-0,29 LSB and the INL is equal to +0,33/-0,26 LSB.Experimental measurements were carried out to determine the performance of the designed ADC. From these tests, non-linearity issues were detected on the output signal of the ADC. These problems in the experimental phase of the design were analyzed, and a hypothesis was proposed to explain them. Based on theoretical and simulation analysis, it was found which the non-linearity issues may have happened owing to the parasitic inductive effect of the wire bonded chip.

show abstract

Section: P/fs [Pj]unclassified

Projeto de um conversor analógico-digital para um receptor UWB aplicado na detecção de câncer de mama em tecnologia CMOS.

Gonzalez¹

View full text Add to dashboard Cite

show abstract

ISFET Array Readout System with Integrated 12 bit A/D Conversion for Lab-on-Chip Applications

Cited by 1 publication

References 11 publications

Projeto de um conversor analógico-digital para um receptor UWB aplicado na detecção de câncer de mama em tecnologia CMOS.

Projeto de um conversor analógico-digital para um receptor UWB aplicado na detecção de câncer de mama em tecnologia CMOS.

Contact Info

Product

Resources

About