Issues on Test Optimization with Known Good Dies and Known Defective Dies ¿ A Statistical Perspective

Abstract

As the timing behavior of the good and defective chips become statistical, the traditional notion that there exists a one-dimensional timing boundary to separate the good and defective behavior may no longer be true. This paper studies issues in test optimization for screening statistical delay defects. After the first silicon tapeout, test data learning based on silicon samples can be utilized to optimize the test set for mass production. This approach depends on the availability of known good and known defective samples. This paper focuses the discussion on silicon sample based test optimization. We relate this problem to binary classification andpattern selection to thefeature selection problem in statistical learning. Experimental results are presented to explain the methodologies and the new concepts.

A Modular Shared L2 Memory Design for 3-D Integration

“…Equation (1) provides an estimation of the yield of the 3-D stack (assuming that the sources of die defects and TSV failures are independent), when known good die testing mechanisms [64] are utilized and failed dies are discarded beforehand. Die yield (Y die ) can be estimated using (2) with a negative binomial model, based on wafer yield (Y wafer ), die area (A die ), and defect density of the wafer (D 0 ) [65].…”

Analyzing the risk of timing modeling based on path delay tests.

“…This work examines one classifier that belongs to the former, the Support Vector Machine (SVM) classifier with linear kernel. SVM was used in an earlier work for delay test optimization [16]. Our use of SVM is entirely different.…”

“…In this paper, we do not discuss the SVM implementation in detail due to space limitation. Interested readers can refer to [16] for the basic concepts of SVM and to [15] for its theory.…”