"It's a small world after all": NoC performance optimization via long-range link insertion

Ogras, Ümit Y.; Mărculescu, Radu

doi:10.1109/tvlsi.2006.878263

Cited by 356 publications

(173 citation statements)

References 41 publications

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“…Moreover, for arbitrary network sizes, randomized networks can be generated with the smaller computational costs than the optimized networks. These topologies can improve bandwidth, scalability, and fault-tolerance for both HPC networks [3]- [5] and on-chip networks [23].…”

Section: Low-latency Random Topologies For Hpc Systemsmentioning

confidence: 99%

A Layout-Oriented Routing Method for Low-Latency HPC Networks

Kawano

Nakahara

Fujiwara

et al. 2017

IEICE Trans. Inf. & Syst.

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SUMMARYEnd-to-end network latency has become an important issue for parallel application on large-scale high performance computing (HPC) systems. It has been reported that randomly-connected inter-switch networks can lower the end-to-end network latency. This latency reduction is established in exchange for a large amount of routing information. That is, minimal routing on irregular networks is achieved by using routing tables for all destinations in the networks. In this work, a novel distributed routing method called LOREN (Layout-Oriented Routing with Entries for Neighbors) to achieve low-latency with a small routing table is proposed for irregular networks whose link length is limited. The routing tables contain both physically and topologically nearby neighbor nodes to ensure livelock-freedom and a small number of hops between nodes. Experimental results show that LOREN reduces the average latencies by 5.8% and improves the network throughput by up to 62% compared with a conventional compact routing method. Moreover, the number of required routing table entries is reduced by up to 91%, which improves scalability and flexibility for implementation.

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Section: Low-latency Random Topologies For Hpc Systemsmentioning

confidence: 99%

A Layout-Oriented Routing Method for Low-Latency HPC Networks

Kawano

Nakahara

Fujiwara

et al. 2017

IEICE Trans. Inf. & Syst.

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“…2-D mesh topology is one of the most practical and extensively used network topologies [31][32][33][34][35] because of its regularity, simple addressing scheme, and multiple source-destination routes [31]. In this mode, packets are divided into flits, which are the smallest unit of flow control and are equal to the network channel width, excluding flit headers, as shown in Fig.…”

Section: Noc-based Test Platformmentioning

confidence: 99%

Hybrid Test Data Transportation Scheme for Advanced NoC-Based SoCs

Ansari¹,

Kim²,

Jung³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Network-on-chip (NoC) has evolved to overcome the issues of traditional bus-based on-chip interconnect. In NoC-reuse as TAM, the test schedulers are constrained with the topological position of cores and test access points, which may negatively affect the test time. This paper presents a scalable hybrid test data transportation scheme that allows to simultaneously test multiple heterogeneous cores of NoC-based SoCs, while reusing NoC as TAM. In the proposed test scheme, single test stimuli set of multiple CUTs is embedded into each flit of the test stimuli packets and those packets are multicast to the targeted CUTs. However, the test response packets of each CUT are unicast towards the tester. To reduce network load, a flit is filled with maximum possible test response sets before unicasting towards the tester. With the aid of Verilog and analytical simulations, the proposed scheme is proved effective and the results are compared with some recent techniques.

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“…Ogras et al [44] showed that a significant reduction in the average packet latency can be achieved by superposing a few long-range links to a standard mesh network. In their approach, the links are however not inserted at random but where they are most useful.…”

Section: B Addressing Interconnect Challenges Bymentioning

confidence: 99%

“…The different system sizes we used were: (1) N = S = [9,14,19,24,29,34,39,44,49,54,59,64] for random multitudes, (2) N = S = [9, 16, 25, 36, 49, 64, 81, 100, 121] for 2D CAs, and (3) N = S = [8,27,64,125] for 3D CAs. Shortest path routing was used.…”

Section: A Experiments 1: System Scalabilitymentioning

confidence: 99%

Nature-inspired interconnects for self-assembled large-scale network-on-chip designs

Teuscher

2007

Chaos: An Interdisciplinary Journal of Nonlinear Science

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Future nano-scale electronics built up from an Avogadro number of components needs efficient, highly scalable, and robust means of communication in order to be competitive with traditional silicon approaches. In recent years, the Networks-on-Chip (NoC) paradigm emerged as a promising solution to interconnect challenges in silicon-based electronics. Current NoC architectures are either highly regular or fully customized, both of which represent implausible assumptions for emerging bottom-up self-assembled molecular electronics that are generally assumed to have a high degree of irregularity and imperfection. Here, we pragmatically and experimentally investigate important design trade-offs and properties of an irregular, abstract, yet physically plausible 3D small-world interconnect fabric that is inspired by modern network-on-chip paradigms. We vary the framework's key parameters, such as the connectivity, the number of switch nodes, the distribution of long-versus short-range connections, and measure the network's relevant communication characteristics. We further explore the robustness against link failures and the ability and efficiency to solve a simple toy problem, the synchronization task. The results confirm that (1) computation in irregular assemblies is a promising and disruptive computing paradigm for self-assembled nano-scale electronics and (2) that 3D small-world interconnect fabrics with a power-law decaying distribution of shortcut lengths are physically plausible and have major advantages over local 2D and 3D regular topologies.

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"It's a small world after all": NoC performance optimization via long-range link insertion

Cited by 356 publications

References 41 publications

A Layout-Oriented Routing Method for Low-Latency HPC Networks

A Layout-Oriented Routing Method for Low-Latency HPC Networks

Hybrid Test Data Transportation Scheme for Advanced NoC-Based SoCs

Nature-inspired interconnects for self-assembled large-scale network-on-chip designs

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