iVAMS 1.0: Polynomial-Metamodel-Integrated Intelligent Verilog-AMS for Fast, Accurate Mixed-Signal Design Optimization

Abstract

Electronic circuit behavioral models built with hardware description/modeling languages such as Verilog-AMS for system-level simulations are typically functional models. They do not capture the physical design (layout) information of the target design. Thus, their applications are limited to early design feasibility studies and/or pre-layout functional verification. Numerous iterations of post-layout design adjustments are usually required to ensure that design specifications are met with the presence of layout parasitics. In this paper a paradigm shift of the current trend is presented that integrates layout-level information (with full parasitics) in Verilog-AMS through metamodels such that systemlevel simulation of a mixed-signal circuit/system is realistic and as accurate as true parasitic netlist simulation. The simulations performed with these parasitic-aware models can be used to estimate system performance without layout iterations. We call this new form of Verilog-AMS as iVAMS (i.e. Intelligent Verilog-AMS). We call this iVAMS 1.0 as it is simple polynomial-metamodel integrated Intelligent Verilog-AMS. As a specific case study, a voltage-controlled oscillator (VCO) Verilog-AMS behavioral model and design flow are proposed to assist fast PLL design space exploration. The PLL simulation employing quadratic metamodels achieves approximately 10× speedup compared to that employing the layout extracted, parasitic netlist. The simulations using this behavioral model attain high accuracy. The observed error for the simulated lock time and average power dissipation are 0.7 % and 3 %, respectively. This behavioral metamodel approach bridges the gap between layout-accurate but fast simulation and design space exploration. The proposed method also allows much shorter design verification and optimization to meet stringent time-to-market requirements. In the PLL optimization case study, 46 % PLL power reduction was achieved using a differential evolution algorithm and the proposed layout-accurate behavioral model. Compared to the optimization using the layout netlist, the runtime using the behavioral model is reduced by 88.9 %. To the best of the authors' knowledge this is the first approach that brings layout-level accuracy to system-level design exploration and is applied towards mixed-signal design exploration.