JHDLBits: The Merging of Two Worlds

Poetter, Alexandra; Hunter, Jesse; Patterson, Cameron; Athanas, Peter; Nelson, Brent; Steiner, Neil

doi:10.1007/978-3-540-30117-2_43

Cited by 8 publications

(5 citation statements)

References 5 publications

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“…However, they will never provide the fast reconfiguration that is possible in a memory-based system, short of an in-situ bitstream reconfiguration approach [11,12].…”

Section: Related Work In Hardware Idsmentioning

confidence: 99%

Regular Expression Software Deceleration for Intrusion Detection Systems

Baker

Jung

Prasanna

2006

2006 International Conference on Field Programmable Logic and Applications

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The use of reconfigurable hardware for network security applications has recently made great strides as FPGA devices have provided larger and faster resources. Regular expressions have become a necessary and basic capability of Intrusion Detection Systems, but their implementation tends to be expensive in terms of memory cost and time performance. This work provides an architecture that reduces the exponential NFA to DFA conversion cost to a linear growth for many expressions.By handling the timing and integration of the regular expression-based rules in a custom microcontroller, the memory costs are reduced and the capabilities are increased over a DFA-only solution. Both the microcontroller and its associated DFA are implemented on the FPGA. The patterns and software are stored using run-time programmable memory tables. This allows on-the-fly modification to the regular expressions.This paper presents the design details of the regular expression microcontroller and its integration to the DFA state machines. The types of expressions that the system can handle efficiently are discussed as well as the outstanding problems that continue to challenge the community.

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“…However, they will never provide the fast reconfiguration that is possible in a memory-based system, short of an in-situ bitstream reconfiguration approach [11,12].…”

Section: Related Work In Hardware Idsmentioning

confidence: 99%

Regular Expression Software Deceleration for Intrusion Detection Systems

Baker

Jung

Prasanna

2006

2006 International Conference on Field Programmable Logic and Applications

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“…Exceptions include circuit generators which directly generate netlists or other design files. For example, [22] describes a tool which directly generates EDIF, while the work in [23] investigated direct bitstream construction, bypassing conventional implementation tools.…”

Section: Configuration Generationmentioning

confidence: 99%

Design, Debug, Deploy: The Creation of Configurable Computing Applications

Nelson

Hutchings

Wirthlin

2008

J Sign Process Syst Sign Image Video Technol

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Configurable Computing Machines (CCMs) are computing machines based on reconfigurable circuit technology such as field programmable gate-arrays. Early researchers recognized CCMs as a new, flexible, and powerful class of computer. The earliest CCMs featured rudimentary but significant integrated design, debug, and deployment (runtime) environments. This paper reviews those environments and the contributions they made and considers the progress made over the past 20 years in providing support for the "3 D's" of configurable computing application development: design, debug, and deployment. It then introduces an integrated CAD framework for the creation of CCM CAD tools and describes a series of experiments in creating such a CAD tool suite -the JHDL system. The paper reviews lessons learned from that work and concludes by discussing the role integrated design, debug, and runtime environments will play in future CCM-based systems.

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“…Many projects that generate or manipulate bitstreams use the JBits API to abstract the bitstream manipulation. For instance, JHDLBits [Poetter et al 2004a[Poetter et al , 2004b is a language bridge between JHDL [Bellows and Hutchings 1998] and JBits that allows applications running in JHDL to handle dynamic reconfiguration. JPG [Raghavan and Sutton 2002] is another tool that uses JBits and the Xilinx Description Language (XDL) representation to generate partial bitstreams.…”

Section: Related Workmentioning

confidence: 99%

Logarithmic-Time FPGA Bitstream Analysis

Bergeron

Perron

Feeley

et al. 2011

ACM Trans. Reconfigurable Technol. Syst.

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Just-In-Time (JIT) compilation is frequently used in software engineering to accelerate program execution. Parts of the code are translated to machine code at runtime to speedup their execution by exploiting local and dynamic information of the computation. Modern FPGAs manufactured by Xilinx allow partial and dynamic configuration. Such features make them eligible platforms for JIT hardware compilation. Nevertheless, this has not been achieved until now because the mapping between a bitstream and the programmable points inside these FPGAs is not documented. In this article, we propose a methodology to retrieve the relevant information in logarithmic time per bit by methodically using the tools distributed by Xilinx. We give a practical case study which details the analysis of a Virtex-II Pro FPGA bitstream. The mapping of CLBs, BRAMs, and multipliers has been fully determined. Thanks to this information, we have been able to prototype tools in the fields of reverse mapping FPGA bitstreams, low-level simulation, and custom placeand-route. Finally preliminary results demonstrate that a processor embedded in an FPGA can compile, place, and route arithmetic and logic expressions inside the FPGA within a few milliseconds.

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JHDLBits: The Merging of Two Worlds

Cited by 8 publications

References 5 publications

Regular Expression Software Deceleration for Intrusion Detection Systems

Regular Expression Software Deceleration for Intrusion Detection Systems

Design, Debug, Deploy: The Creation of Configurable Computing Applications

Logarithmic-Time FPGA Bitstream Analysis

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