2016
DOI: 10.4236/cs.2016.75045
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Jitter Reduced Self Biased PLLs—A Systematic Simulation Study

Abstract: The self biased Phase Locked Loop (PLL) has become a default choice for clock generation in many microprocessors. In today's scenario, the processor cores are made to operate at rapidly varying combinations of clock frequencies and very low supply voltages. Though the traditional self biased PLL is still being widely used with hardly any modification, it is becoming imperative to take a relook at the design aspects of these PLLs with respect to their jitter performance. This paper presents a systematic simulat… Show more

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