Junction profiles of sub keV ion implantation for deep sub-quarter micron devices

Abstract

Ultra shallow junctions <500 hi with steep profiles 4nmldecade are required for device technologies 50.13 pm as outlined by the recent ITRS Roadmap. For a $In junction such profiles can be obtained using sub-keV B ion implantation since both the projected range and more importantly the transient enhanced diffusion are significantly reduced at lower energies. State-of-the-art high current implanters utilize deceleration mode typically for sub 1 keV implantation in order to increase the beam current and production wafer throughput. Such a mode contains a very low level of energy contamination. This level is measured for sub keV B implants in the Quantum Leap and factors affecting the level of contamination are studied. Spike and soak annealing reduces the effect of the energy contamination on junction profile and depth. The effect of energy contamination on device performance such as Lff, VT and b s A~ is simulated using ISE TCAD. I.

Converting SOI to sSOI through Amorphization and Crystallization: Material Analysis and Device Demonstration

“…Second, regarding the amorphous/crystal interface roughness, peak-to-valley roughness between 1 and 8 nm can be found in literature depending on implantation conditions. 11 Note that these observations are made on surface amorphous layers, with a/c interface located in the tail (bottom) of the defect distribution. In our case, with a buried amorphous layer, the a/c interface is at the top of the defect distribution.…”