Junctionless MOSFETs with laterally graded-doping channel for analog/RF applications

Mohamed, Mohamed; Jo, Michael; Xu, Ruimin

doi:10.1007/s10825-013-0478-3

Cited by 37 publications

(16 citation statements)

References 36 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The JL concept was later implemented in several devices, such as gate-all-around, FinFET, tunnel FET, thin film transistor, double gate and tri-gate devices. These devices have strong immunity against subthreshold operations like subthreshold slope (SS) and leakage current when scaled down to nanolevels [2,3]. High-performance thin film transistor devices are favorable for Active-Matrix Organic Light-Emitting Diode (AMOLED) and Active-Matrix Liquid-Crystal Display (AMLCD).…”

Section: Introductionmentioning

confidence: 99%

Influence of Tunable Work Function on SOI-based DMG Multi-channel Junctionless Thin Film Transistor

Kumar¹,

Pravin²

2021

J. Nano- Electron. Phys.

View full text Add to dashboard Cite

This paper focuses on the effects occurring due to the inclusion of multi-channel titanium nitride (TiN) material in a dual metal gate (DMG) junctionless (JL) thin film transistor. Two nanosheets have been implemented in a JL tri-gate transistor, which is separated by the gate oxide layer and surrounded by the gate layer. The thickness of TiN material placed in between the gate oxide and gate layer helps in tuning the work function of the gate. The comparison has been done between single channel with single metal gate, double channel with single metal gate, double channel with DMG and double channel with DMG and TiN. Strains have been created in the devices by implementing TiN and DMG. An improvement of 31 % in the output current has been obtained using DMG double channel device when compared with single gate single channel device. The comparison has been carried out in Sentaurus technology computer aided design (TCAD). The drift diffusion model, the mobility model, which includes the effects of doping concentration and electric field, the bandgap narrowing model and the Shockley-Read-Hall recombination model have been used to calculate outputs. The proposed structure acquires higher transconductance values than normal tri-gate devices. It has been verified that when varying the TiN thickness, the potential has been tuned. Due to the tuning of the work function, the performance of the device has been improved.

show abstract

Section: Introductionmentioning

confidence: 99%

Influence of Tunable Work Function on SOI-based DMG Multi-channel Junctionless Thin Film Transistor

Kumar¹,

Pravin²

2021

J. Nano- Electron. Phys.

View full text Add to dashboard Cite

show abstract

“…Moreover, enhancement in early voltage and intrinsic voltage gain are attained due to low electric field at drain end of oxide interface. In [20], the effect of laterally graded channel doping in double gate junctionless MOSFETs for analog/RF applications was presented. Besides, high cutoff frequency and high intrinsic voltage gain are obtained.…”

Section: Introductionmentioning

confidence: 99%

Analog/RF Performance of Triple Material Gate Stack-Graded Channel Double Gate-Junctionless Strained-silicon MOSFET with Fixed Charges

Suddapalli¹,

Joseph²,

Chintala³

et al. 2021

Preprint

View full text Add to dashboard Cite

In this paper, analog/radio frequency (RF) electrical characteristics of triple material gate stack-graded channel double gate-Junctionless (TMGS-GCDG-JL) strained-silicon (s-Si) MOSFET with fixed charges is analyzed with the help of Sentaurus TCAD. By varying the various device parameters, the analog/RF performance of the proposed TMGS-GCDG-JL s-Si MOSFET is evaluated in terms of early voltage, transconductance generation factor (TGF), voltage gain, unity current gain frequency ( ft ), unity power gain frequency (fmax ), and gain transconductance frequency product (GTFP). The results confirm that the proposed TMGS-GCDG-JL s-Si MOSFET has superior analog/RF performance compared to the gate stack-graded channel double gate-junctionless (GS-GCDG-JL) s-Si MOSFET. However, the proposed device has less transconductance and less output conductance in comparison with the GS-GCDG-JL s-Si MOSFET in strong inversion region, and reverse trend follows in sub-threshold region.

show abstract

“…Junctionless configuration is another alternative solution to allow the continuity of transistor's shrinkage without degrading the device performance [35][36][37][38]. This configuration has been aggressively studied and applied by many researchers due to its simplified fabrication process [39].…”

Section: Introductionmentioning

confidence: 99%

Design Consideration and Impact of Gate Length Variation on Junctionless Strained Double Gate MOSFET

2019

IJRTE

View full text Add to dashboard Cite

Aggressive scaling of Metal-oxide-semiconductor Field Effect Transistors (MOSFET) have been conducted over the past several decades and now is becoming more intricate due to its scaling limit and short channel effects (SCE). To overcome this adversity, a lot of new transistor structures have been proposed, including multi gate structure, high-k/metal gate stack, strained channel, fully-depleted body and junctionless configuration. This paper describes a comprehensive 2-D simulation design of a proposed transistor that employs all the aforementioned structures, named as Junctionless Strained Double Gate MOSFETs (JLSDGM). Variation in critical design parameter such as gate length (L g ) is considered and its impact on the output properties is comprehensively investigated. The results shows that the variation in gate length (L g ) does contributes a significant impact on the drain current (I D ), on-current (I ON ), off-current (I OFF ), I ON /I OFF ratio, subthreshold swing (SS) and transconductance (g m ). The JLSDGM device with the least investigated gate length (4nm) still provides remarkable device properties in which both I ON and g m (max) are measured at 1680 µA/µm and 2.79 mS/µm respectively. Engineering (FKEKK), UTeM. Her research interest includes process and device simulation of nanoscale MOSFETs device, advanced CMOS design, optimization approach (DOE) and process parameter variability. Z. A. F. M. Napiah received the B.Eng. degree in electrical engineering and the M.Eng. degree in Microelectronic from Universiti Teknologi Malaysia (UTM). He received the Ph.D. degree in Microelectronics from Kanawa University, Japan. He is currently a senior lecturer at Faculty of Electronic and Computer Engineering (FKEKK), UTeM. His research interest includes process and device simulation of MOSFET device, advanced CMOS design and CMOS based Photodetector and Photoreceiver.

show abstract

Junctionless MOSFETs with laterally graded-doping channel for analog/RF applications

Cited by 37 publications

References 36 publications

Influence of Tunable Work Function on SOI-based DMG Multi-channel Junctionless Thin Film Transistor

Influence of Tunable Work Function on SOI-based DMG Multi-channel Junctionless Thin Film Transistor

Analog/RF Performance of Triple Material Gate Stack-Graded Channel Double Gate-Junctionless Strained-silicon MOSFET with Fixed Charges

Design Consideration and Impact of Gate Length Variation on Junctionless Strained Double Gate MOSFET

Contact Info

Product

Resources

About