KARL and ABL

Hartenstein, Reiner W.

doi:10.1007/978-94-011-1914-6_16

Cited by 2 publications

(1 citation statement)

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“…A trailblazing idea for TRS use in microchip design [16] has been delayed by 30 years. All Term Rewriting Systems (TRS) in EDA are used for verification, which means bottom-up approaches.…”

Section: Using Term Rewriting (Tr) For Synthesismentioning

confidence: 99%

The tunnel vision syndrome: Massively delaying progress

Hartenstein

2013

2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors

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Professor, IEEE fellow, SDPS fellow, FPL fellow, TU Kaiserslautern, Karlsruhe Institute of Technology (KIT), UnBIntroduction. Despite of acceleration factors by up to several orders of magnitude the FPGA share in the IC market is still below 2%. The multicore and supercomputing dilemma massively reduces programmer productivity and the progress of performance improvement. Predictions are warning that, if current trends continue, the total of all electricity bills spiraling out of control could have serious consequences for the overall affordability of computing. The progress in power-efficient high performance solutions, coming from a few isolated areas, is by far too slow to break current trends. A few "silver bullet results" touting a single facet as the complete answer are far from solving the problem. What is the reason of these slow-down effects? Here the ASAP conference series was always a platform for critical discussions. The following sections illustrate, how the recognition of systolic arrays and term rewriting as fundamentals of datastream-based computing was delayed for decades by the tunnel vision syndrome.

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“…A trailblazing idea for TRS use in microchip design [16] has been delayed by 30 years. All Term Rewriting Systems (TRS) in EDA are used for verification, which means bottom-up approaches.…”

Section: Using Term Rewriting (Tr) For Synthesismentioning

confidence: 99%