Karna: A Gate-Sizing based Security Aware EDA Flow for Improved Power Side-Channel Attack Protection

Slpsk, Patanjali; Vairam, Prasanna Karthik; Rebeiro, Chester; Kamakoti, V.

doi:10.1109/iccad45719.2019.8942173

Cited by 23 publications

(7 citation statements)

References 29 publications

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“…After investigation, it appears that in some cases, the processor stalls for one cycle, which is not taken into account in our model. While we have not yet found out the reason why Key [12] ^ Key [15] (ex0) Key [12] ^ Key [14] (ex1) Key [14] ^ Key [15] (ex2) SBox[Key [12]] (ex3) SBox[Key [14]] (ex4) SBox[Key [15]] (ex5) SBox[Key [12]] ^ SBox[Key [15]] (ex6) SBox[Key [14]] ^ SBox[Key [15]] (ex7) Fig. 9.…”

Section: Accuracy and Exploitabilitymentioning

confidence: 85%

“…Also, when the patching fails, developers are left clueless with the leakage, advocating for a solution able to explain it. On the hardware side, the usage of dedicated logic or design tools can help reduce the sources of potential leakage [12], [13]. Such design-time solutions do not help for existing processors.…”

Section: Related Workmentioning

confidence: 99%

“…However, using it in an attempt to shield from the architecture implementation details is not a solution [11]. A promising approach is to take into account leakage at processor design time [12], [13], but no such leakage-free architecture is available yet. Accurate modelling of leakage sources for an actionable verification of masked software running on generic off-the-shelf processors is still an open research question.…”

Section: Introductionmentioning

confidence: 99%

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ARMISTICE: Microarchitectural Leakage Modeling for Masked Software Formal Verification

Grandmaison¹,

Heydemann

Meunier

2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Side channel attacks are powerful attacks for retrieving secret data by exploiting physical measurements such as power consumption or electromagnetic emissions. Masking is a popular countermeasure as it can be proven secure against an attacker model. In practice, software masked implementations suffer from a security reduction due to a mismatch between the considered leakage sources in the security proof and the real ones, which depend on the micro-architecture. We propose ARMISTICE, a framework for formally verifying the absence of leakage in first-order masked implementations taking into account modelled micro-architectural sources of leakage. As a proof of concept, we present the modelling of an Arm Cortex-M3 core from its RTL description and leakage test vectors, as well as the modelling of the memory of a STM32F1 board, exclusively using leakage test vectors. We show that, with these models, ARMISTICE pinpoints vulnerable instructions in real world masked implementations and helps the design of masked software implementations which are practically secure.

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Section: Accuracy and Exploitabilitymentioning

confidence: 85%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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ARMISTICE: Microarchitectural Leakage Modeling for Masked Software Formal Verification

Grandmaison¹,

Heydemann

Meunier

2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…The use of CAD tools for gate-level simulation is adopted in ACA [16] and Karna [13]. ACA finds the leaky gates in the gate-level netlist and replaces them locally with hardened structures.…”

Section: Related Workmentioning

confidence: 99%

Leverage the Average: Averaged Sampling in Pre-Silicon Side-Channel Leakage Assessment

Kiaei,

Liu,

Schaumont

2022

Preprint

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Pre-silicon side-channel leakage assessment is a useful tool to identify hardware vulnerabilities at design time, but it requires many high-resolution power traces and increases the power simulation cost of the design. By downsampling and averaging these highresolution traces, we show that the power simulation cost can be considerably reduced without significant loss of side-channel leakage assessment quality. We introduce a theoretical basis for our claims. Our results demonstrate up to 6.5-fold power-simulation speed improvement on a gate-level side-channel leakage assessment of a RISC-V SoC. Furthermore, we clarify the conditions under which the averaged sampling technique can be successfully used. CCS CONCEPTS• Security and privacy → Hardware security implementation; • Hardware → Best practices for EDA.

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“…For example, the popular algorithmic masking scheme [175] results in over 3× of performance degradation. In the recent years, the need for incorporating security countermeasures in low-cost embedded hardware has motivated the emergence of efficient countermeasures like [176]- [178], where the algorithms available in the commercial EDA flows are leveraged to reduce area and delay overheads of these countermeasures.…”

Section: Side Channel Protection Techniquesmentioning

confidence: 99%

An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools

Chang

Sengupta

et al. 2021

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Karna: A Gate-Sizing based Security Aware EDA Flow for Improved Power Side-Channel Attack Protection

Cited by 23 publications

References 29 publications

ARMISTICE: Microarchitectural Leakage Modeling for Masked Software Formal Verification

ARMISTICE: Microarchitectural Leakage Modeling for Masked Software Formal Verification

Leverage the Average: Averaged Sampling in Pre-Silicon Side-Channel Leakage Assessment

An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools

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