2009 IEEE International Interconnect Technology Conference 2009
DOI: 10.1109/iitc.2009.5090359
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Key Process steps for high reliable SiOCH low-k dielectrics for the sub 45nm technology nodes

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Cited by 3 publications
(2 citation statements)
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“…However, the low-k materials are characterized by poor mechanical, thermal, and electrical properties in comparison with silicon dioxide, [2]. Some of the process steps such as chemical mechanical planarization (CMP) and plasma etch can potentially damage the dielectric sub-surfaces regions, generating charge carrier traps and assisting the conduction, [3]. As a result, the IC chips integrated with the copper/low-k interconnects tend to be vulnerable to TDDB failure.…”
Section: Introductionmentioning
confidence: 99%
“…However, the low-k materials are characterized by poor mechanical, thermal, and electrical properties in comparison with silicon dioxide, [2]. Some of the process steps such as chemical mechanical planarization (CMP) and plasma etch can potentially damage the dielectric sub-surfaces regions, generating charge carrier traps and assisting the conduction, [3]. As a result, the IC chips integrated with the copper/low-k interconnects tend to be vulnerable to TDDB failure.…”
Section: Introductionmentioning
confidence: 99%
“…However, it has been reported that this has some risks such as the degradation of dielectric breakdown characteristics and time-dependent dielectric breakdown (TDDB) reliability. [10][11][12][13] In this paper, we demonstrate the effects of Cu interconnect integration using direct CMP process on porous low-k film. Reliability was improved by using a porous lowk film with higher resistance against CMP damage in addition to setting soft CMP conditions to reduce the damage.…”
Section: Introductionmentioning
confidence: 99%