Killi: Runtime Fault Classification to Deploy Low Voltage Caches without MBIST

Ganapathy, Shrikanth; Kalamatianos, John; Beckmann, Bradford M.; Raasch, Steven E.; Szafaryn, Lukasz G.

doi:10.1109/hpca.2019.00046

Cited by 7 publications

(8 citation statements)

References 24 publications

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“…Recent work [6], [42] demonstrates that bit flips in SRAMs increase exponentially when reducing voltage below V min . The authors of [5] study the impact of bit flips in different layers of DNNs, showing severe accuracy degradation.…”

Section: Low-voltage Random Bit Errors In Dnn Acceleratorsmentioning

confidence: 99%

“…3 (right). Nevertheless, there is generally an "inherited" distribution of bit cell failures across voltages: as described in [42], if a bit error occurred at a given voltage, it is likely to occur at lower voltages, as made explicit in Fig. 3.…”

Section: Low-voltage Induced Random Bit Errorsmentioning

confidence: 99%

“…Work such as [5], [19] model the effect of low-voltage induced bit errors using two parameters: the probability p flt of bit cells in accelerator memory, being faulty and the probability p err that a faulty bit cell results in a bit error on access. Following measurements in works such as [4], [42], we assume that these errors are not transient errors by setting p err = 100% such that the overall probability of bit errors is p := p flt • p err = p flt . In doing so, we consider the worst-case where faulty bit cells always induce bit errors.…”

Section: Low-voltage Induced Random Bit Errors In Quantized Dnn Weightsmentioning

confidence: 99%

“…For a specific voltage, the resulting bit cell failures can be assumed to be random and independent of each other. We assume a bit to be faulty with probability p flt increasing exponentially with decreased voltage [4], [5], [6], [42]. Furthermore, the faulty bits for p flt ≤ p flt can be assumed to be a subset of those for p flt .…”

Section: Low-voltage Induced Random Bit Errors In Quantized Dnn Weightsmentioning

confidence: 99%

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Random and Adversarial Bit Error Robustness: Energy-Efficient and Secure DNN Accelerators

Stutz¹,

Chandramoorthy²,

Hein³

et al. 2021

Preprint

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Deep neural network (DNN) accelerators received considerable attention in recent years due to the potential to save energy compared to mainstream hardware. Low-voltage operation of DNN accelerators allows to further reduce energy consumption significantly, however, causes bit-level failures in the memory storing the quantized DNN weights. Furthermore, DNN accelerators have been shown to be vulnerable to adversarial attacks on voltage controllers or individual bits. In this paper, we show that a combination of robust fixed-point quantization, weight clipping, as well as random bit error training (RANDBET) or adversarial bit error training (ADVBET) improves robustness against random or adversarial bit errors in quantized DNN weights significantly. This leads not only to high energy savings for low-voltage operation as well as low-precision quantization, but also improves security of DNN accelerators. Our approach generalizes across operating voltages and accelerators, as demonstrated on bit errors from profiled SRAM arrays, and achieves robustness against both targeted and untargeted bit-level attacks. Without losing more than 0.8%/2% in test accuracy, we can reduce energy consumption on CIFAR10 by 20%/30% for 8/4-bit quantization using RANDBET. Allowing up to 320 adversarial bit errors, ADVBET reduces test error from above 90% (chance level) to 26.22% on CIFAR10.

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Section: Low-voltage Random Bit Errors In Dnn Acceleratorsmentioning

confidence: 99%

Section: Low-voltage Induced Random Bit Errorsmentioning

confidence: 99%

Section: Low-voltage Induced Random Bit Errors In Quantized Dnn Weightsmentioning

confidence: 99%

Section: Low-voltage Induced Random Bit Errors In Quantized Dnn Weightsmentioning

confidence: 99%

See 2 more Smart Citations

Random and Adversarial Bit Error Robustness: Energy-Efficient and Secure DNN Accelerators

Stutz¹,

Chandramoorthy²,

Hein³

et al. 2021

Preprint

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“…As general purpose GPUs (GPGPUs) are becoming increasingly susceptible to transient hardware faults (soft errors) often from cosmic radiation [1] or from operating under low voltage [2], their reliable operation is of critical importance. With GPGPUs becoming omnipresent in fields such as highperformance computing (HPC), artificial intelligence, deep learning, virtual/augmented reality, and safety critical systems such as autonomous vehicles [3]- [10], transient hardware faults can lead to bit flips in storage devices including the register file and DRAM.…”

Section: Introductionmentioning

confidence: 99%

Enabling Software Resilience in GPGPU Applications via Partial Thread Protection

Yang

Nie

Jog

et al. 2021

2021 IEEE/ACM 43rd International Conference on Software Engineering (ICSE)

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Graphics Processing Units (GPUs) are widely used by various applications in a broad variety of fields to accelerate their computation but remain susceptible to transient hardware faults (soft errors) that can easily compromise application output. By taking advantage of a general purpose GPU application hierarchical organization in threads, warps, and cooperative thread arrays, we propose a methodology that identifies the resilience of threads and aims to map threads with the same resilience characteristics to the same warp. This allows engaging partial replication mechanisms for error detection/correction at the warp level. By exploring 12 benchmarks (17 kernels) from 4 benchmark suites, we illustrate that threads can be remapped into reliable or unreliable warps with only 1.63% introduced overhead (on average), and then enable selective protection via replication to those groups of threads that truly need it. Furthermore, we show that thread remapping to different warps does not sacrifice application performance. We show how this remapping facilitates warp replication for error detection and/or correction and achieves an average reduction of 20.61% and 27.15% execution cycles, respectively comparing to standard duplication/triplication.

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