Kinematics calculation of minimally invasive surgical robot based on FPGA

Jiang, Ziyang; Dai, Yu; Zhang, Jianxun; Su, He

doi:10.1109/robio.2017.8324667

Cited by 5 publications

(6 citation statements)

References 10 publications

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“…Given this scenario, by adding the t s FK module time that calculates forward kinematics with the IK module, the total time resulting from both implementations reaches 265 ns, according to Table 4. Hence, the hardware presented in the work here developed achieved a 7.54 × speedup over the model presented in [29].…”

Section: Fk-hmdmentioning

confidence: 84%

“…Similarly, an FPGA implementation of forward and inverse kinematics for a 7-DoF device was presented in [29], however, only 3-DoF required to control the device movement were implemented in hardware. The proposal used a 32-bit fixed point representation and a CORDIC was used to execute the trigonometric functions.…”

Section: Related Workmentioning

confidence: 99%

“…Differently from previous works (Table 4), in [29], the authors present unique hardware for calculating forward and inverse kinematics together. In the proposed model, the 32bit fixed-point representation was used.…”

Section: Fk-hmdmentioning

confidence: 99%

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Reconfigurable Computing Applied to Latency Reduction for the Tactile Internet

Junior,

Torquato,

Mahmoodi

et al. 2020

Preprint

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Tactile internet applications allow robotic devices to be remotely controlled over a communication medium with an unnoticeable time delay. In a bilateral communication, the acceptable round trip latency is usually in the order of 1 ms up to 10 ms depending on the application requirements. It is estimated that 70% of the total latency is generated by the communication network, and the remaining 30% is produced by master and slave devices. Thus, this paper aims to propose a strategy to reduce the 30% of total latency that is produced by such devices. The strategy is to apply reconfigurable computation using FPGAs to minimize the execution time of device-associated algorithms. With this in mind, this work presents a hardware reference model for modules that implement nonlinear positioning and force calculations as well as a tactile system formed by two robotic manipulators. In addition to presenting the implementation details, simulations and experimental tests are performed in order to validate the proposed model. Results associated with the FPGA sampling rate, throughput, latency and post-synthesis occupancy area are analyzed.

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Section: Fk-hmdmentioning

confidence: 84%

Section: Related Workmentioning

confidence: 99%

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Reconfigurable Computing Applied to Latency Reduction for the Tactile Internet

Junior,

Torquato,

Mahmoodi

et al. 2020

Preprint

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show abstract

“…Differently from previous works ( Table 4 ), in [ 35 ], the authors present unique hardware for calculating forward and inverse kinematics together. In the proposed model, the 32-bit fixed-point representation was used.…”

Section: Resultsmentioning

confidence: 99%

“…Similarly, an FPGA implementation of forward and inverse kinematics for a 7-DoF device was presented in [ 35 ]; however, only 3-DoF required to control the device movement were implemented in hardware. The proposal used a 32-bit fixed point representation and a CORDIC was used to execute the trigonometric functions.…”

Section: Related Workmentioning

confidence: 99%

FPGA Applied to Latency Reduction for the Tactile Internet

José

Silva

Torquato

et al. 2022

Sensors

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Tactile internet applications allow robotic devices to be remotely controlled over a communication medium with an unnoticeable time delay. In bilateral communication, the acceptable round trip latency is usually 1 ms up to 10 ms, depending on the application requirements. The communication network is estimated to generate 70% of the total latency, and master and slave devices produce the remaining 30%. Thus, this paper proposes a strategy to reduce 30% of the total latency produced by such devices. The strategy is to use FPGAs to minimize the execution time of device-associated algorithms. With this in mind, this work presents a new hardware reference model for modules that implement nonlinear positioning and force calculations and a tactile system formed by two robotic manipulators. In addition to presenting the implementation details, simulations and experimental tests are performed in order to validate the hardware proposed model. Results associated with the FPGA sampling rate, throughput, latency, and post-synthesis occupancy area are analyzed.

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Hardware Accelerated Inverse Kinematics for Low Power Surgical Manipulators

Tkachenko¹,

Song

2020

2020 International Conference on Advanced Robotics and Intelligent Systems (ARIS)

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Kinematics calculation of minimally invasive surgical robot based on FPGA

Cited by 5 publications

References 10 publications

Reconfigurable Computing Applied to Latency Reduction for the Tactile Internet

Reconfigurable Computing Applied to Latency Reduction for the Tactile Internet

FPGA Applied to Latency Reduction for the Tactile Internet

Hardware Accelerated Inverse Kinematics for Low Power Surgical Manipulators

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