2010
DOI: 10.1166/jnn.2010.2263
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Kinetic Monte Carlo (kMC) Simulation of Carbon Co-Implant on Pre-Amorphization Process

Abstract: We report our kinetic Monte Carlo (kMC) study of the effect of carbon co-implant on the pre-amorphization implant (PAL) process. We employed BCA (Binary Collision Approximation) approach for the acquisition of the initial as-implant dopant profile and kMC method for the simulation of diffusion process during the annealing process. The simulation results implied that carbon co-implant suppresses the boron diffusion due to the recombination with interstitials. Also, we could compare the boron diffusion with carb… Show more

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“…Referring to Figure 8, we see that the proposed device has a maximum impact ionization as low as 2 44 × 10 16 cm −3 s −1 at V DS = 70 V, whereas the conventional one has a value of 6 69 × 10 19 cm −3 s −1 at the same condition, which implies that the proposed LDMOS reduces the carrier generation near the drain at high V GS and V DS to ensure high on-state breakdown voltage. [9][10][11][12][13] Figure 9 shows the simulated device structure and the impact ionization rates at V DS = 30, 50, and 70 V. The high impact ionization spot moves from the gate to the drain due to the high level of current density. As illustrated in Figure 9, the proposed LDMOS reduces the carrier generation near the drain at high V GS and V DS to ensure high on-state breakdown voltage.…”
Section: Resultsmentioning
confidence: 99%
“…Referring to Figure 8, we see that the proposed device has a maximum impact ionization as low as 2 44 × 10 16 cm −3 s −1 at V DS = 70 V, whereas the conventional one has a value of 6 69 × 10 19 cm −3 s −1 at the same condition, which implies that the proposed LDMOS reduces the carrier generation near the drain at high V GS and V DS to ensure high on-state breakdown voltage. [9][10][11][12][13] Figure 9 shows the simulated device structure and the impact ionization rates at V DS = 30, 50, and 70 V. The high impact ionization spot moves from the gate to the drain due to the high level of current density. As illustrated in Figure 9, the proposed LDMOS reduces the carrier generation near the drain at high V GS and V DS to ensure high on-state breakdown voltage.…”
Section: Resultsmentioning
confidence: 99%