L G 55 nm T‐gate InGaN / GaN channel based high electron mobility transistors for stable transconductance operation

The impact of scaling on the gate all around the nanosheet field effect transistor (NSFET) was studied in detail at sub-5-nm nodes for digital and analog/RF applications. When LG is scaled from 20 to 5 nm, ION is improved by 2.1×, IOFF increases by three orders of magnitude, SS increases by 27%, DIBL is increased by 4×, and a Vth roll off of 41 mV is noticed. Further, an enhancement of 3.65× was noticed in cut-off frequency (fT) with scaling of LG from 20 to 5 nm. The complimentary metal oxide semiconductor (CMOS) inverter and ring oscillator’s performance was studied in detail with LG scaling. With LG scaling from 20 to 5 nm, the inverter performance metrics like switching current is increased by 3.87×, propagation delay (τP), energy delay product and power delay product are reduced by 65%, 5.5× and 1.95×, respectively. Moreover, the ring oscillator offers superior performance with an oscillation frequency of 98.05 GHz when LG is scaled to 5nm, which is 157% more than fOSC at LG of 20 nm. Thus the analyses reveal the scaling capability of NSFET at both device and circuit levels for sub-5-nm nodes.

mentioning

confidence: 99%

Impact of Scaling on Nanosheet FET and CMOS Circuit Applications

Neelam

Sreenivasulu

Pothupogu

2023

“…Moreover, as the transistor scaled down to lower technology nodes, the drain and source came into close proximity and the drain started to influence the channel in addition to the gate. 13 The phenomenon led to various short channel effects (SCEs), 14,15 such as drain induced barrier lowering (DIBL), degradation in subthreshold swing, threshold voltage roll-off, 16,17 etc.…”

mentioning

confidence: 99%

Spacer Engineering on Nanosheet FETs towards Device and Circuit Perspective

Kumari,

Sreenivasulu,

Ajayan

et al. 2023

For the first time, a nanosheet field effect transistor (NS FET) performance is demonstrated by incorporating various device engineering at both device and circuit levels. Various device topologies like lightly-doped drain/source, underlap, single and dual-k spacer are explored and the performance is compared with conventional NS FET. The NS FET with dual-k spacer is able to reduce the off current by 13.6× compared to the traditional NS FET. Further, the dual-k spacer offered good electrostatic performance and high switching ratio. Moreover, the analog/RF figures of merit are assessed for various device configurations. Though the dual-k spacer outperforms in terms of DC and analog metrics, the conventional NS FET can offer better RF metrics owing to the high current. Further, circuit level analysis is carried out using the Cadence tool for mixed circuit applications. The crucial circuits for IC design such as inverter, ring oscillator and common source (CS) amplifier are designed and evaluated the performance. The NS FET with dual-k spacer offers a gain of 1.815 for the CS amplifier and an oscillation frequency of 34.09 GHz for the 3-stage ring oscillator. The results will give insights into the performance of NS FET with various device architectures

“…But making FinFETs with thinner and taller fins is a difficult operation, and their small bases can lead to design problems. [17][18][19] To address all these problems of traditional FETs, GAA structures-Nanosheet (NS), and Nanowire (NW) are introduced. In GAA configurations, the channel is surrounded by the gate in all the dimensions, thereby improving the gate controllability over the device to a remarkable extent and improving sub-threshold performance.…”

mentioning

confidence: 99%

Nanosheet Field Effect Transistor Device and Circuit Aspects for Future Technology Nodes

Sreenivasulu

Chavva

et al. 2023

Moore's law states that the technical innovations are being absorbed already. The device's controllability has dramatically improved since moving from a straightforward metal oxide semiconductor field effect transistor (FET) constructed with a single control gate to one with many control gates. Here, the device-level simulation of vertically stacked GAA nanosheet FET is performed, for which the various geometrical variations are calibrated to examine the impact of these geometrical variations on the device's performance. The most prominent parameters like ION, IOFF, SS, DIBL, switching ratio, and threshold voltage values are analyzed. For the device to be considered to have better performance ION should be maximum, IOFF should be minimum. Hence, to obtain this, the thickness of the nanosheet is varied on the scale of 5 to 9 nm, and the width is varied from 10 to 50 nm. The device simulation and analysis are performed using the Visual TCAD - 3D Cogenda tool.