LADA methodologies to localize embedded memory failure

Yeoh, B.L.; Thor, MH; Gan, LS; Chan, Yi‐Hsin; Goh, S.H.

doi:10.1109/ipfa55383.2022.9915715

Cited by 1 publication

(2 citation statements)

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“…This technique could be used to analyze speed path-related faults. Yeoh et al [51] presented a laser-assisted device alteration (LADA) methodology to localize soft and hard failures in memory. Using LADA methodology, the author presented a case study to show memory fail-to-pass region.…”

Section: Hardware Methods For Defect Localizationmentioning

confidence: 99%

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Memory built-in self-repair and correction for improving yield: a review

Sontakke,

Atchina

2024

IJECE

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Nanometer memories are highly prone to defects due to dense structure, necessitating memory built-in self-repair as a must-have feature to improve yield. Today’s system-on-chips contain memories occupying an area as high as 90% of the chip area. Shrinking technology uses stricter design rules for memories, making them more prone to manufacturing defects. Further, using 3D-stacked memories makes the system vulnerable to newer defects such as those coming from through-silicon-vias (TSV) and micro bumps. The increased memory size is also resulting in an increase in soft errors during system operation. Multiple memory repair techniques based on redundancy and correction codes have been presented to recover from such defects and prevent system failures. This paper reviews recently published memory repair methodologies, including various built-in self-repair (BISR) architectures, repair analysis algorithms, in-system repair, and soft repair handling using error correcting codes (ECC). It provides a classification of these techniques based on method and usage. Finally, it reviews evaluation methods used to determine the effectiveness of the repair algorithms. The paper aims to present a survey of these methodologies and prepare a platform for developing repair methods for upcoming-generation memories.

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Section: Hardware Methods For Defect Localizationmentioning

confidence: 99%

“…They will also be seen in upcoming technologies. Hardware-based techniques such as PEM [50] and LADA [51] could be used to complement the BISR-based hypothesis. These two techniques together could be used to finalize localization before the start of physical defect analysis.…”

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confidence: 99%

Memory built-in self-repair and correction for improving yield: a review

Sontakke,

Atchina

2024

IJECE

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LADA methodologies to localize embedded memory failure

Cited by 1 publication

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Memory built-in self-repair and correction for improving yield: a review

Memory built-in self-repair and correction for improving yield: a review

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