Laguerre-gram reduced order modeling applied to VLSI circuit interconnects

Abstract

Reduced order modeling has become a vital tool for decreasing computational cost in time domain simulations. In this paper we present a Laguerre-Gram model-order reduction technique applied to admittance matrices of circuit interconnect lines. We show reduction results for a single line and for a system of two coupled lines but also an iterative solution for obtaining better low order approximations of delayed signals.

Low Complexity Equivalent Circuit Models for VLSI Interconnects

“…Our team has explained y(2//)(s) ) avec 1<A<.p 1<,u<m the details of the Laguerre-Gram MOR method [1] as well as D(s) certain improvements we may bring when it is specifically For reasons of simplicity in the case of VLSI interconnects used for interconnect lines. A frequency approach on the we use admittance matrices [2], [5].…”

“…1 a, each element yi s102 of the 1z quadripole is realised according to Foster's canonical form. For a 4x4 admittance matrix (two coupled lines) [5] we have the general design in figure lb and it is quite obvious how it should evolve for larger matrices.…”