LAOCOÖN: A Run-Time Monitoring and Verification Approach for Hardware Trojan Detection

Danger, Jean‐Luc; Fribourg, Laurent; Kühne, Ulrich; Naceur, Maha

doi:10.1109/dsd.2019.00047

Cited by 3 publications

(3 citation statements)

References 32 publications

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“…In [74], it is proposed to identify high-level and critical behavioral invariants of a processor inspired from assertion-based verification, and a Hardware Property Checker (HPC) is designed that verifies these invariants at run-time. Another approach uses temporal logic assertions to automatically synthesize monitor circuits [75]. A run-time detection of the A2 Trojan [27], [28] is proposed in [76] that works by guarding a set of concerned victim signals and initiating a hardware interrupt request when abnormal toggling events occur.…”

Section: Run-time Monitors For Ht Detectionmentioning

confidence: 99%

Run-Time Hardware Trojan Detection in Analog and Mixed-Signal ICs

Pavlidis¹,

Faehn

Louërat³

et al. 2022

2022 IEEE 40th VLSI Test Symposium (VTS)

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Hardware Trojan (HT) insertion is a major security threat for electronic components that demand a high trust level. Several HT attack mechanisms have been demonstrated to date, and several HT prevention and detection countermeasures have been proposed to thwart HT attacks. Given the multitude of HT attack mechanisms, run-time monitors for HT detection are used as a last line of defense. In this paper, we propose a run-time monitoring methodology for HT attack mechanisms affecting the analog and mixed-signal (AMS) sections of an Integrated Circuit (IC). The methodology is based on the Symmetry-based Built-In Self-Test (SymBIST) principle that relies on distributing invariances across the IC and continuously checking for their compliance. Detection of various HT attacks are demonstrated on a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) IP at transistor-level.

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Section: Run-time Monitors For Ht Detectionmentioning

confidence: 99%

Run-Time Hardware Trojan Detection in Analog and Mixed-Signal ICs

Pavlidis¹,

Faehn

Louërat³

et al. 2022

2022 IEEE 40th VLSI Test Symposium (VTS)

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“…Ngo et al 20 implemented a hardware runtime property checker to verify important design properties. Danger et al 30 presented automatic monitoring generation to validate formal properties. Bilzor et al 31 discussed a method to create assertion‐based dynamic checkers as part of the processor's design.…”

Section: Literature Reviewmentioning

confidence: 99%

“…However, the hardware property checkers have some limitations 21,22,30 . For example, checkers cannot prevent a HT malicious activity, rather other system resources (e.g., processor) should manage the response in the event of a HT detection.…”

Section: Literature Reviewmentioning

confidence: 99%

Hardware Trojan detection for lightweight ciphers implemented on field‐programmable gate arrays using the replay algorithm

Abed

Mohd

Hayajneh

et al. 2021

Circuit Theory & Apps

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Summary Hardware Trojans (HTs) are malicious and intentional modification of the hardware design, embedded by an adversary to leak sensitive data, modify functionality, or cause malfunction. Lightweight ciphers are designed for resource‐constrained devices (RCDs) to balance resources and security, but often targeted by HTs. This work aims to create a trusted lightweight cipher design and detect complex sequential HTs using a runtime monitoring method with minimal resource overhead. The novelty of the approach is that it combines full or partial temporal redundancy, resource minimization, and runtime monitoring. The algorithm employs temporal redundancy, by executing a first run of the cipher, and then replays the cipher fully (ReplayN method) or partially (ReplayN/2 method). A mismatch indicates HT activity, and a third replay is executed to determine the correct results. The ReplayN/2 algorithm further optimizes time and energy by limiting replay to the second half of the cipher rounds. The proposed method is compared with other existing methods including triple modular redundancy (TMR), adapted triple modular redundancy (ATMR), and reverse‐function redundancy (RFR). All methods were implemented in field‐programmable gate array (FPGA) technology. Implementation performance metrics were measured and compared, including resource utilization (i.e., logical elements [LEs]), power, energy (E), and speed (i.e., Fmax). The results show that the proposed algorithm outperforms existing methods in most of the metrics. In terms of speed and area, the replay algorithm is faster by 24% and reduces total LEs by 42% when compared with existing methods. Regarding power, replay algorithm reduces power by 45% when compared with TMR and ATMR. With respect to energy, replay methods reduce energy by an average of 6% when compared with TMR and ATMR. The ReplayN/2 reduces energy by an average 15% when compared with TMR and ATMR. Based on the normalE×LE (i.e., energy × area) metric, ReplayN/2 is the top performing method as it balances area and energy metrics. Using normalE×LEnormalFmax metric, the replay methods are the best performing methods as they best balance area, energy, and speed. Also, based on ThroughputLE2 metric, the replay methods are the top performing methods.

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Runtime hardware Trojan detection by reconfigurable monitoring circuits

Fani

Zamani

2022

J Supercomput

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LAOCOÖN: A Run-Time Monitoring and Verification Approach for Hardware Trojan Detection

Cited by 3 publications

References 32 publications

Run-Time Hardware Trojan Detection in Analog and Mixed-Signal ICs

Run-Time Hardware Trojan Detection in Analog and Mixed-Signal ICs

Hardware Trojan detection for lightweight ciphers implemented on field‐programmable gate arrays using the replay algorithm

Runtime hardware Trojan detection by reconfigurable monitoring circuits

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